UPD17P136ACT datasheet(55/292 Pages) NEC

55 / 292 page

CHAPTER 6 STACK

6.3 ADDRESS STACK REGISTERS (ASRs)

Five 11-bit address stack registers (ASRs) are provided as shown in Figure 6-1. The functions of these registers

are as follows:

•

Store a return address when the CALL addr or CALL @AR instruction is executed, when the first instruction

cycle of the “MOVT DBF, @AR” instruction is executed, or when an interrupt is accepted.

•

Store the contents of an address register (AR) when the PUSH AR instruction is executed. The ASR to which

the data is to be stored is specified by decrementing the value of the stack pointer (SP) by one when the

instruction is executed.

•

Restore the contents of the ASR (return address) specified by the stack pointer to the program counter and

increment the value of the stack pointer by one when the RET or RETSK instruction is executed, when the second

instruction cycle of the “MOVT DBF, @AR” instruction is executed, or when the RETI instruction is executed.

•

Transfer the value of the ASR specified by the stack pointer to an address register and decrement the value

of the stack pointer by one when the POP AR instruction is executed.

Caution If the stack pointer underflows as a result of executing the CALL addr or CALL @AR instruction

or servicing an interrupt, it is assumed that a hang-up occurs. Consequently, the internal reset

signal is generated, the hardware is initialized, and the program is started from address 0000H.

Remark The size of the ASR differs depending on the model. The

µPD17134A and 17135A have five 10-bit

ASRs, while the

µPD17136A, 17137A, 17P136A, and 17P137A have five 11-bit ASRs.

6.4 INTERRUPT STACK REGISTERS (INTSKs)

Three 5-bit interrupt stack registers (INTSKs) are provided as shown in Figure 6-1. The functions of these registers

are as follows:

•

Five flags (BCD, CMP, CY, Z, and IXE) in the program status word (PSWORD) in the system register (SYSREG)

to be explained shortly are saved to the INTSK when an interrupt occurs. After the flags have been saved, all

the bits of the BANK and PSWORD are cleared to 0.

•

The contents of INTSK are restored to the PSWORD when the RETI instruction is executed.

•

INTSK saves data each time an interrupt has been accepted.

Caution If interrupts are accepted exceeding 3 levels, the first data is lost.

UPD17P136ACT Datasheet(PDF) 55 Page - NEC