UPD17P136ACT datasheet(62/292 Pages) NEC

62 / 292 page

CHAPTER 7 SYSTEM REGISTER (SYSREG)

7.2 ADDRESS REGISTER (AR)

7.2.1 Address Register Configuration

Figure 7-3 shows the configuration of the address register.

As shown in Figure 7-3, the address register consists of the 16 bits in address 74H to 77H (AR3 to AR0) of the

system register. However, since the high-order 5 or 6 bits are always set to 0, the address register is actually 11 or

10 bits. When the system is reset, all 16 bits of the address register are reset to 0.

Figure 7-3. Address Register Configuration

Note

This bit is fixed to 0 in the case of the

µPD17134A and µPD17135A.

7.2.2 Address Register Functions

The address register is used to specify an address in program memory when executing an indirect branch

instruction (BR @AR), indirect subroutine call (CALL @AR) or table reference (MOVT DBF, @AR). The address

Items (1) to (4) explain address register operation during execution of each instruction.

The address register can be incremented by using the dedicated increment instruction (INC AR).

(1) Table reference (MOVT DBF, @AR)

When the “MOVT DBF, @AR” instruction is executed, the data in program memory (16-bit data) located

at the address specified by the value in the address register is read into the data buffer (addresses

0CH to 0FH of BANK0).

(2) Stack manipulation instructions (PUSH AR, POP AR)

When the PUSH AR instruction is executed, the stack pointer (SP) is first decremented and then the address

When the POP AR instruction is executed, the contents of the address stack pointed to by the stack pointer

is transferred to the address register and then the stack pointer is incremented.

Also see CHAPTER 6 STACK.

0000

AR1

AR0

AR2

AR3

76H

77H

75H

74H

Address

Name

Address register (AR)

Symbol

Bit

Data

Initial value when

reset

(AR)

Note

UPD17P136ACT Datasheet(PDF) 62 Page - NEC

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