UPD17P136ACT datasheet(134/292 Pages) NEC

134 / 292 page

CHAPTER 13 PERIPHERAL HARDWARE

115

13.1.2 Operation of 8-Bit Timers/Counters

(1) Count register

The count register of timers 0 and 1 is an 8-bit up counter whose initial value is 00H, and is incremented each

time a count pulse has been input.

The count register is initialized to 00H in the following cases.

(1) When this product is reset (refer to CHAPTER 17 RESET).

(2) When the contents of the 8-bit modulo register and the value of the count register coincide, and the

comparator generates a coincidence signal.

(3) In the case of timer 0, when “1” is written to TM0RES of the register file.

In the case of timer 1, when “1” is written to TM1RES of the register file.

(2) Modulo register

The modulo register of timers 0 and 1 determines the count value of the count register and its initial value is

set to FFH.

A value is set to the modulo register by using the PUT instruction via DBF (data buffer).

(3) Comparator

The comparator of timers 0 and 1 outputs a coincidence signal when the value of the count register and the

value of the modulo register coincide. If the value of the modulo register is the initial value FFH, for example,

the comparator outputs the coincidence signal when the count register counts 256.

The coincidence signal output from the comparator clears the contents of the count register to 0, and

automatically sets interrupt request flags (IRQTM0 and IRQTM1) to “1”. If the EI instruction (that enables

accepting interrupts) is executed, and if the interrupt enable flags (IPTM0 and IPTM1) are set at this time,

interrupts are accepted. When an interrupt has been accepted, the interrupt request flag (IRQTM0 or IRQTM1)

is cleared to “0”, and program execution branches to a specified interrupt routine.

13.1.3 Selecting Count Pulse

The count pulse for timer 0 is selected by TM0CK0 and TM0CK1.

As the count pulse, a pulse resulting from dividing the system clock (fX) by 256, 64, or 16, or an external count pulse

input from the INT pin can be selected.

At reset, fX/256 is selected as a count pulse because TM0CK0 = 0 and TM0CK1 = 0.

The count pulse for timer 1 is selected by TM1CK0 and TM1CK1.

As the count pulse, a pulse resulting from dividing fX by 1024, 512, or 256, or the count up signal from timer 0 can

be selected.

Timer 1 is also used to generate oscillation stabilization time on power application or at reset. Therefore, the initial

values are TM1CK0 = 0 and TM1CK1 = 0, and fX/512 is selected as the count pulse.

Because TM1EN = 1 as the initial condition, the

µPD17134A subseries starts program execution from address

0000H after it has been reset at fX = 8 MHz and after about 16.4 ms (about 65.5 ms at 2 MHz) (refer to CHAPTER

17 RESET).

UPD17P136ACT Datasheet(PDF) 134 Page - NEC