AM6421 datasheet(135/237 Pages) TI

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7.10.5 Peripherals

7.10.5.1 CPSW3G

For more details about features and additional description information on the device Gigabit Ethernet MAC, see

the corresponding sections within Section 6.3, Signal Descriptions and Section 8, Detailed Description.

7.10.5.1.1 CPSW3G MDIO Timing

Table 7-18, Table 7-19, Table 7-20, and Figure 7-20 present timing conditions, requirements, and switching

characteristics for CPSW3G MDIO.

Table 7-18. CPSW3G MDIO Timing Conditions

PARAMETER

MIN

MAX

UNIT

INPUT CONDITIONS

SRI

Input slew rate

0.9

3.6

V/ns

OUTPUT CONDITIONS

Output load capacitance

470

Table 7-19. CPSW3G MDIO Timing Requirements

see Figure 7-20

NO.

PARAMETER

MIN

MAX

UNIT

MDIO1 tsu(MDIO_MDC)

Setup time, MDIO[x]_MDIO valid before MDIO[x]_MDC high

MDIO2 th(MDC_MDIO)

Hold time, MDIO[x]_MDIO valid after MDIO[x]_MDC high

Table 7-20. CPWS3G MDIO Switching Characteristics

see Figure 7-20

NO.

PARAMETER

MIN

MAX

UNIT

MDIO3 tc(MDC)

Cycle time, MDIO[x]_MDC

400

MDIO4 tw(MDCH)

Pulse Duration, MDIO[x]_MDC high

160

MDIO5 tw(MDCL)

Pulse Duration, MDIO[x]_MDC low

160

MDIO7 td(MDC_MDIO)

Delay time, MDIO[x]_MDC low to MDIO[x]_MDIO valid

-150

150

MDIO3

MDIO1

MDIO2

MDIO7

MDIO4

MDIO5

MDIO[x]_MDC

MDIO[x]_MDIO

(input)

MDIO[x]_MDIO

(output)

CPSW2G_MDIO_TIMING_01

Figure 7-20. CPSW3G MDIO Timing Requirements and Switching Characteristics

7.10.5.1.2 CPSW3G RMII Timing

Table 7-21, Table 7-22, Figure 7-21, Table 7-23, Figure 7-22 Table 7-24, and Figure 7-23 present timing

conditions, requirements, and switching characteristics for CPSW3G RMII.

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SPRSP56 – JANUARY 2021

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