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7.10.4.2 Output Clocks

The device provides several system clock outputs. Summary of these output clocks are as follows:

• MCU_SYSCLKOUT0

– SYSCLK0 of from the MCU_PLL controller is divided by 6 and then sent out of the device as a LVCMOS

clock signal (MCU_SYSCLKOUT0). This signal can be used to test if the MCU chip clock is functioning or

not.

• MCU_OBSCLK0

– On the clock output MCU_OBSCLK0, oscillators and PLLs clocks can be observed for tests and debug.

• SYSCLKOUT0

– SYSCLK0 from the MAIN_PLL controller is divided by 6 and then sent out of the device as a LVCMOS

clock signal (SYSCLKOUT0). This signal can be used to test if the MAIN chip clock is functioning or not.

• CLKOUT0

– Reference clock output

• OBSCLK0

– On the clock output OBSCLK0, oscillators and PLLs clocks can be observed for tests and debug.

7.10.4.3 PLLs

Power is supplied to the Phase-Locked Loop circuits (PLLs) by internal regulators that derive their power from

off-chip power-sources.

There is one PLL in the MCU domain:

• MCU0_PLL

There are six PLLs in the MAIN domain:

• ARM0_PLL

• MAIN_PLL

• PER0_PLL

• PER1_PLL

• DDR PLL

• R5F PLL

Note

For more information, see:

• Device Configuration / Clocking / PLLs section in the device TRM.

• Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem - Gigabit

(PRU_ICSSG) section in the device TRM.

Note

The input reference clock (MCU_OSC0_XI / MCU_OSC0_XO) is specified and the lock time is

ensured by the PLL controller, as documented in the Device Configuration chapter in the device TRM.

AM6442, AM6441, AM6421

AM6412, AM6411

SPRSP56 – JANUARY 2021

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