AM6421 datasheet(136/237 Pages) TI

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Table 7-21. CPSW3G RMII Timing Conditions

PARAMETER

MIN

MAX

UNIT

INPUT CONDITIONS

SRI

Input slew rate

VDDSHVx(1) = 1.8V

0.18

0.54

V/ns

VDDSHVx(1) = 3.3V

0.4

1.2

V/ns

OUTPUT CONDITIONS

Output load capacitance

(1)

x = 0 - 5, where x indicates the respective IO power rail. Refer to Section 6.2 for more information on IO power rail assinments.

Table 7-22. RMII[x]_REF_CLK Timing Requirements – RMII Mode

see Figure 7-21

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

RMII1

tc(REF_CLK)

Cycle time, RMII[x]_REF_CLK

19.999

20.001

RMII2

tw(REF_CLKH)

Pulse Duration, RMII[x]_REF_CLK High

RMII3

tw(REF_CLKL)

Pulse Duration, RMII[x]_REF_CLK Low

RMII[x]_REF_CLK

RMII2

RMII3

RMII1

Figure 7-21. CPSW3G RMII[x]_REF_CLK Timing Requirements – RMII Mode

Table 7-23. RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RX_ER Timing Requirements – RMII Mode

see Figure 7-22

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

RMII4

tsu(RXD-REF_CLK)

Setup time, RMII[x]_RXD[1:0] valid before RMII[x]_REF_CLK

tsu(CRS_DV-REF_CLK)

Setup time, RMII[x]_CRS_DV valid before RMII[x]_REF_CLK

tsu(RX_ER-REF_CLK)

Setup time, RMII[x]_RX_ER valid before RMII[x]_REF_CLK

RMII5

th(REF_CLK-RXD)

Hold time RMII[x]_RXD[1:0] valid after RMII[x]_REF_CLK

th(REF_CLK-CRS_DV)

Hold time, RMII[x]_CRS_DV valid after RMII[x]_REF_CLK

th(REF_CLK-RX_ER)

Hold time, RMII[x]_RX_ER valid after RMII[x]_REF_CLK

RMII4

RMII5

RMII[x]_

REF CLK

RMII[x]_RXD[1:0], RMII[x]_CRS_DV,

RMII[x]_RX_ER

Figure 7-22. CPSW3G RMII[x]_RXD[1:0], RMII[x]_CRS_DV, RMII[x]_RX_ER Timing Requirements – RMII

Mode

AM6442, AM6441, AM6421

AM6412, AM6411

SPRSP56 – JANUARY 2021

www.ti.com

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Product Folder Links: AM6442 AM6441 AM6421 AM6412 AM6411

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