AM6421 datasheet(212/237 Pages) TI

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8.4.2 Peripherals

8.4.2.1 ADC

The analog-to-digital converter (ADC) module is an eight-channel general purpose analog-to-digital converter,

which supports 12-bit conversion samples from an analog front end (AFE).

There are two ADC modules in the device.

For more information, see Analog-to-Digital Converter (ADC) section in Peripherals chapter in the device TRM.

8.4.2.2 ATL

The ATL module supports the following features:

• One ATL module, containing four ATL instances, for HD Radio support and asynchronous sample rate

conversion assistance

• Each instance tracks the time error between two syncs (local audio word select [AWS] and baseband word

select [BWS])

• Each instance selects between 28 mux choices for BWS and 30 mux choices for AWS.

• Each instance generates modulated ATCLK clock signals with software-initiated pulse stealing. The intention

is to use these clocks to derive audio output bit clock on MCASP

• Selection between ATL_VCLK clock or functional ATL_PCLK to run error counting timers and to derive

modulated ATCLK clock outputs.

• Clock and reset management: Receives clock and reset signals from the device PSC module. The ATL

module receives hardware reset.

• Power management: The ATL belongs to the PD0 power domain.

• Local software reset

The ATL module not supports the following features:

• Smart ATL_CLK_STOP

• ATL_MOD_OUT[3:0] clock outputs

For more information, see Audio Tracking Logic (ATL) section in Peripherals chapter in the device TRM.

8.4.2.3 AASRC

The AASRC module supports the following main features:

• High performance Asynchronous Sample Rate Converter with 140dB Signal-to-Noise (SNR)

• Up to 8 input and output stereo streams (16 audio channels)

• 4 input and output clock zones

• Support for input and output audio sample rates from 8 kHz to 216 kHz

• Automatically sensing/detection of input sample frequencies

• Attenuation of sampling clock jitter

• 16-, 18-, 20-, 24-bit data input/output

• Input/output sampling ratios from 16:1 to 1:16

• 32-sample input and output FIFO for each channel with independently configurable thresholds

• Group mode, where multiple AASRC blocks use the same timing loop for input or output

• Linear phase FIR filter

• Controllable soft mute

• Separate DMA events for input and output, for each channel and group

• Interrupts for input, output, and error for channels and groups of channels

• Channels belonging in an input/output clock zone may be configured and managed as a group or as

individual streams

• Independent clock generator for each input and output clock zone

• Independent rate and stamp generator for each input and output clock zone

The AASRC module has the following main constraints:

AM6442, AM6441, AM6421

AM6412, AM6411

SPRSP56 – JANUARY 2021

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