LAN7430SLASHY9X datasheet(20/77 Pages) MICROCHIP

20 / 77 page

LAN7430/LAN7431

DS00002631D-page 20

 2018-2019 Microchip Technology Inc.

TX Negative

PCIE_TX_M

PCIe Serial Data Output negative.

Serial differential output link in the PCIe interface running

at 2.5 GT/s.

A series capacitor in the range of 100nF to 200nF is

required.

RX Positive

PCIE_RX_P

PCIe Serial Data Input positive.

Serial differential input link in the PCIe interface running

at 2.5 GT/s.

RX Negative

PCIE_RX_M

PCIe Serial Data Input negative.

Serial differential input link in the PCIe interface running

at 2.5 GT/s.

External Refer-

ence Clock

Positive

PCIE_CLK_P

PCIe Differential Reference Clock In positive

This pin receives a 100 MHz differential clock input.

External Refer-

ence Clock

Negative

PCIE_CLK_M

PCIe Differential Reference Clock In negative

This pin receives a 100 MHz differential clock input.

External Refer-

ence Resistor

RESREF

This pin should be connect to ground through a 200 ohm

1% 100 ppm / C resistor.

Wake up

WAKE#

IS / OD4

Wake

This signal is driven low when the device detects a

wakeup.

In OBFF mode, OBFF events are signaled using the

WAKE#

pin as an input.

Note:

When the device is powered down, this pin is

isolated from the PCIe bus and does not

present any significant loading or provide any

drive.

PCIe Reset

PERST#

Power and Clock Good Indication

The PERST# signal indicates that both PCIe power and

clock are available.

Note:

When the device is powered down, this pin is

isolated from the PCIe bus and does not

present any significant loading or provide any

drive.

Clock Request

CLKREQ#

IS / OD4

Clock Request

The CLKREQ# signal is used to power manage the Link

clock. It is also used for L1 power management Sub state

control.

Note:

When the device is powered down, this pin is

isolated from the PCIe bus and does not

present any significant loading or provide any

drive.

TABLE 3-3:

PIN DESCRIPTIONS (CONTINUED)

Name

Symbol

Buffer

Type

Description

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