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LAN7430/Y9X Datasheet(PDF) 57 Page - Microchip Technology |
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LAN7430/Y9X Datasheet(HTML) 57 Page - Microchip Technology |
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57 / 77 page ![]() 2018-2019 Microchip Technology Inc. DS00002631D-page 57 LAN7430/LAN7431 7.6.3 POWER-ON CONFIGURATION STRAP TIMING Figure 7-4 illustrates the configuration strap timing requirements, in relation to power-on, for applications where RESET_N is not used at power-on. The operational level (Vopp) for the external power supply is detailed in Section 7.2, "Operating Conditions**," on page 48. FIGURE 7-3: POWER SEQUENCE TIMING (EXTERNAL REGULATORS) TABLE 7-11: POWER SEQUENCING TIMING VALUES Symbol Description Min Typ Max Units tpon Power supply turn on time 50 ms tpoff Power supply turn off time 500 ms FIGURE 7-4: POWER-ON CONFIGURATION STRAP TIMING TABLE 7-12: POWER-ON CONFIGURATION STRAP TIMING Symbol Description Min Typ Max Units tcsh Configuration strap hold after external power supply at operational level 22 ms todad Output drive after straps latched 3 µs VDDVARIO, VDDVARIO_B VDD_SW_IN, VDD_REG_IN, VDD_OTP, AVDDH_1, AVDDH_2 tpon tpoff VDD12CORE, AVDD12, AVDDL_1, AVDDL_2, VPH, VPTX, VP All External Power Supplies Vopp Configuration Strap Pins tcsh Output Drive todad |
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