LAN7430SLASHY9X datasheet(46/77 Pages) MICROCHIP

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LAN7430/LAN7431

DS00002631D-page 46

 2018-2019 Microchip Technology Inc.

6.14

Integrated Voltage Regulators

The LAN7430/LAN7431 includes both a switching regulator and LDO to facilitate ease of integration and to allow oper-

ation off of a single power supply.

6.14.1

SWITCHING REGULATOR

The switching regulator supplies 1.2 volts to the main core digital logic, the I/O pads and the Gigabit Ethernet PHY’s

digital logic, all via the VDD12CORE inputs. It also supplies the 1.2V power to the Gigabit Ethernet PHY’s analog sec-

tions and the PCIe PHY’s analog, digital and transmit sections, all via external connections. It operates from a 1.8V to

3.3V input supply and can supply up to 600mA output current.

When the VDD12_SW_FB pin is connected to the 1.2V regulated voltage, the switching regulator is enabled and

receives 1.8V to 3.3V on the VDD_SW_IN pin.

The switching regulator requires an external LC filter to generate the 1.2V regulated voltage. A 3.3uH inductor should

be connected between the switching regulator’s output, VDD12_SW_OUT pin, and the 1.2V regulated supply. A 10uF

ceramic capacitor, along with a noise filtering 0.1uF ceramic, should be connected from the 1.2V regulated supply to

ground.

Over-Current Protection and Short-Circuit Protection are supported.

The switching regulator can be disabled to allow for an external 1.2V supply. When the VDD12_SW_FB pin is connected

to the VDD_SW_IN pin, the switching regulator is disabled. However, 1.8V to 3.3V must still be supplied to the

VDD_SW_IN pin.

Refer to Section 4.0, "Power Connectivity" for additional details.

6.14.2

LOW-DROPOUT REGULATOR

The LDO regulator supplies 2.5 volts to the PCIe PHY and the Gigabit Ethernet PHY, all via external connections. It

operates from a 3.3V input supply and can supply up to 250mA output current. The Gigabit Ethernet PHY can alterna-

tively be powered by an external 3.3V supply.

When the VDD_REG_IN pin is connected to 3.3V, the LDO regulator is enabled. A 1.0 uF 0.1-ohm ESR capacitor must

be connected to the VDD25_REG_OUT pin.

The LDO regulator can be bypassed to allow for an external 2.5V supply. When the VDD25_REG_OUT pin is connected

to the VDD_REG_IN pin, the LDO regulator is disabled. However, 2.5V must still be supplied to the VDD_REG_IN pin.

Refer to Section 4.0, "Power Connectivity" for additional details.

6.15

JTAG

The integrated IEEE 1149.1 compliant TAP Controller supports boundary scan and various test modes via the JTAG test

port. The interface consists of four pins (TDO, TDI, TCK and TMS) and includes a state machine, data register array,

and an instruction register. The JTAG pins are described in Table 3-3, “Pin Descriptions,” on page 16. The JTAG inter-

face conforms to the IEEE Standard 1149.1 - 2001 Standard Test Access Port (TAP) and Boundary-Scan Architecture.

All input and output data is synchronous to the TCK test clock input. TAP input signals TMS and TDI are clocked into

the test logic on the rising edge of TCK, while the output signal TDO is clocked on the falling edge.

The JTAG functionality is selected when the TEST pin is asserted. The implemented IEEE 1149.1 instructions and their

op codes are shown in Table 6-3. The JTAG IDs for each version of the device are shown in Table 6-4. Refer to Section

7.6.8, "JTAG Timing" for detailed JTAG timing specifications.

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