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LAN7430/Y9X Datasheet(PDF) 9 Page - Microchip Technology |
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LAN7430/Y9X Datasheet(HTML) 9 Page - Microchip Technology |
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9 / 77 page ![]() 2018-2019 Microchip Technology Inc. DS00002631D-page 9 LAN7430/LAN7431 An internal block diagram of the LAN7430/LAN7431 is shown in Figure 2-1. The following system-level block diagrams detail the LAN7430/LAN7431 in typical applications. FIGURE 2-1: LAN7430/LAN7431 BLOCK DIAGRAM LAN7430/ 1 DMA & FIFO Controller Tx Ch0 RxCh 0...3 GPIO 1588 OTP Memory EEPROM Loader PCIe Endpoint Controller Tx Offload Engine Ethernet PHY ++802.3az (EEE) PCIe v3.1 2.5 GT / s PHY ++L1SS 1v2 Switching Regulator 2v5 LDO Regulator VDDVARIO JTAG TAP Rx Filtering Engine Checksum Offload VLAN Priority | RSS NS / ARP AOAC Ethernet MAC with IEEE1588 2008 Integrated Clock Tree 25 MHz MII / RGMII + (LAN7431) Single 3v3 Supply |
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