VR4102 datasheet(25/701 Pages) NEC

25 / 701 page

LIST OF TABLES (2/4)

Table. No.

Title

Page

3-9

Shift Instruction (Extended ISA)..............................................................................................................

3-10

Multiply/Divide Instructions .....................................................................................................................

3-11

Multiply/Divide Instructions (Extended ISA)............................................................................................

3-12

Number of Stall Cycles in Multiply and Divide Instructions.....................................................................

3-13

Number of Delay Slot Cycles in Jump and Branch Instructions .............................................................

3-14

Jump Instructions ...................................................................................................................................

3-15

Branch Instructions .................................................................................................................................

3-16

Branch Instructions (Extended ISA)........................................................................................................

3-17

Special Instructions ................................................................................................................................

3-18

Special Instructions (Extended ISA) .......................................................................................................

3-19

System Control Coprocessor (CP0) Instructions ....................................................................................

4-1

Description of Pipeline Activities during Each Stage ..............................................................................

101

4-2

Correspondence of Pipeline Stage to Interlock and Exception Condition ..............................................

110

4-3

Description of Pipeline Exception ...........................................................................................................

111

4-4

Pipeline Interlock ....................................................................................................................................

111

5-1

Comparison of useg and xuseg ..............................................................................................................

122

5-2

32-bit and 64-bit Supervisor Mode Segments ........................................................................................

126

5-3

32-bit Kernel Mode Segments ................................................................................................................

130

5-4

64-bit Kernel Mode Segments ................................................................................................................

132

5-5

Cacheability and the xkphys Address Space .........................................................................................

133

5-6

VR4102 Physical Address Space............................................................................................................

136

5-7

ROM Addresses (when using 16-bit data bus) .......................................................................................

137

5-8

ROM Addresses (when using 32-bit data bus) .......................................................................................

137

5-9

Internal I/O Space 1................................................................................................................................

139

5-10

Internal I/O Space 2................................................................................................................................

139

5-11

DRAM Addresses (when using 16-bit data bus).....................................................................................

140

5-12

DRAM Addresses (when using 32-bit data bus).....................................................................................

140

5-13

Cache Algorithm .....................................................................................................................................

145

5-14

Mask Values and Page Sizes .................................................................................................................

147

6-1

CP0 Exception Processing Registers .....................................................................................................

159

6-2

Cause Register Exception Code Field....................................................................................................

166

6-3

64-Bit Mode Exception Vector Base Addresses .....................................................................................

174

6-4

32-Bit Mode Exception Vector Base Addresses .....................................................................................

174

6-5

Exception Priority Order..........................................................................................................................

176

10-1

BCU Registers ........................................................................................................................................

235

10-2

Address Bit Correspondence between ADD Bus and External Devices ................................................

246

10-3

Address Connection Table with External Devices ..................................................................................

246

10-4

Access Size Restrictions for Address Spaces ........................................................................................

247

10-5

Summary of ROM Modes .......................................................................................................................

248

10-6

Example of Bit Inversion in Data in VR4102 and at DATA [15:0] Pins ....................................................

250

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