ST25DV04KC datasheet(74/203 Pages) STMICROELECTRONICS

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6.5.1

Random address read

A dummy write is first performed to load the address into this address counter (as shown in Figure 35. Read

mode sequences) but without sending a Stop condition. Then, the bus master sends another Start condition (aka

reStart), and repeats the device select code, with the Read/Write bit (RW) set to 1. The device acknowledges this,

and outputs the contents of the addressed byte. The bus master must not acknowledge the byte, and terminates

the transfer with a Stop condition.

6.5.2

Current address read

For the Current address read operation, following a Start condition, the bus master only sends a device select

code with the Read/Write bit (RW) set to 1. The device acknowledges this, and outputs the byte addressed by

the internal address counter. The counter is then incremented. The bus master terminates the transfer with a Stop

condition, as shown in the figure below, without acknowledging the byte.

Figure 35. Read mode sequences

Dev sel *

Byte addr

Dev sel

Data out 1

Data out N

Current address read

Dev sel

Data out

Random address read

Dev sel *

Data out

Sequential current read

Data out N

Dev sel *

Byte addr

Sequential random read

Dev sel *

Data out1

ACK

R/W

NO ACK

ACK

R/W

ACK

R/W

ACK

NO ACK

R/W

NO ACK

ACK

R/W

ACK

R/W

ACK

NO ACK

6.5.3

Sequential read access

This operation can be used after a Current address read or a Random address read. The bus master does

acknowledge the data byte output, and sends additional clock pulses so that the device continues to output the

next byte in sequence. To terminate the stream of bytes, the bus master must not acknowledge the last byte, and

must generate a Stop condition, as shown in Figure 35. Read mode sequences.

ST25DV04KC ST25DV16KC ST25DV64KC

I²C read operations

DS13519 - Rev 3

page 74/203

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