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AM2434BSDFHIALVR Datasheet(PDF) 5 Page - Texas Instruments |
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AM2434BSDFHIALVR Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 242 page ![]() 3.1 Functional Block Diagram Figure 3-1 is the functional block diagram for the device. Industrial Connectivity PRU-ICSS(Gb) System Memory Security A 243x M intro_001 2 MB SRAM with ECC DDR4/LPDDR4 with inline ECC 2x MMCSD AES MD5 SHA 3DES PKA DRBG Secure Boot System Services 12x GP Timers 4x WWDT Sync Manager 3x EQEP 3x ECAP 9x EPWM 4x I2C GPIO 5x MCSPI 1x ADC 7x UART PCIe 1x Single lane Gen 2 GPMC / ELM 8x FSI OSPI or QSPI 2x CAN-FD 2x GMAC Encoder with 9x ∆ ∑ PRU-ICSS(Gb) 2x GMAC Encoder with 9x ∆ ∑ 1x USB 3.1 DRD 2-port Gb Ethernet General Connectivity 2x I2C GPIO 2x MCSPI 2x UART Isolated Connectivity (A) (for use with Cortex-M4F) 128KB TCM Arm ® Cortex -R5F ® 128KB TCM Arm ® Cortex -R5F ® Arm ® Cortex -R5F ® Arm ® Cortex -R5F ® Arm ® ® Cortex -M4F 256KB SRAM Real-time cores Isolated core (A) A. Isolation of peripherals and M4F core is an optional feature. MCU domain resources are shared across SoC when in non-isolated configuration. B. USB3.1 and PCIe share a common SerDes lane. Figure 3-1. Functional Block Diagram www.ti.com AM2434, AM2432, AM2431 SPRSP65C – APRIL 2021 – REVISED MARCH 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: AM2434 AM2432 AM2431 |
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