AM2434BSDFHIALVR datasheet(7/242 Pages) TI

7 / 242 page

4 Revision History

Changes from July 16, 2021 to March 14, 2022 (from Revision B (July 2021) to Revision C

(March 2022))

Page

• (Features): Deleted Trusted Execution Environment (TEE). Arm TrustZone® support for Cortex-A cores only

bullets. Not supported on AM243x devices........................................................................................................ 1

• (Device Information): Added footnote for AM2432_ALV/ALX and AM2431_ALV/ALX device options regarding

pre-production part numbers.............................................................................................................................. 3

• (Device Comparison): Clarified speed grade options for each device. Also clarified functional safety support

and added a note that references the Nomenclature Description table..............................................................8

• (AM243x_ALX Package - Unsupported Interfaces and Signals): Updated table and associated notes...........58

• (Pin Connectivity Requirements [was "Connections for Unused Pins"]): Added new pin connection

requirements and updated SERDES power pin connection requirements to include a condition of device

boundary scan usage....................................................................................................................................... 94

• (Pin Connectivity Requirements): Included VMON connectivity requirements................................................. 94

• (Absolute Maximum Ratings): Replaced free-air in the table description with junction and moved MCU_PORz

from a row of dual-voltage fail-safe pins to its own row.................................................................................... 99

• (Recommended Operating Conditions): Replaced free-air in the table description with junction and added a

note to VDD_MMC0 and VDD_DLL_MMC0...................................................................................................102

• (Recommended Operating Conditions): Combined VDDS_DDR and VDDS_DDR_C into a single row and

added a note that explains these two power rails should be powered from the same source........................102

• Updated the "The voltage at the device ball must never ..." footnote............................................................. 102

• (Speed Grade Maximum Frequency): Added Speed Grade K - ICSSG operating frequency (250 MHz)...... 104

• (Speed Grade Maximum Frequency): Updated Note 1 to reference the AM64x\AM243x DDR Board Design

and Layout Guidelines.................................................................................................................................... 104

• (Fail-Safe Reset Electrical Characteristics): Updated values for VILSS and VIHSS parameters.......................105

• (LVCMOS Electrical Characteristics): Corrected the VOH MIN value for 1.8V Mode...................................... 109

• (Recommended Operating Conditions for OTP eFuse Programming): Replaced free-air in the table

description with junction and changed operating temperature description to remove ambient and replace with

junction. Also removed the recommendation for using a specific power management solution..................... 111

• (ALV Package Thermal Resistance Characteristics): Updated TBD values in the table with actual values... 112

• (ALX Package Thermal Resistance Characteristics): Updated TBD values in the table with actual values...112

• (System Timing): Removed the maximum input slew rate requirement from the Systems Timing Conditions

table................................................................................................................................................................ 118

• (Clock Timing): Added MCU_EXT_REFCLK0 to the Clock Timing Requirements, and added

MCU_SYSCLKOUT0 and MCU_OBSCLK0 to the Clock Switching Characteristics......................................123

• (MCU_OSC0 Internal Oscillator Clock Source): Added a note to define the maximum ESRxtal value based on

the Cshunt parameter....................................................................................................................................... 125

• (MCU_OSC0 Start-up Time): Updated signal names in figure....................................................................... 125

• (CPSW3G): Added IOSET information...........................................................................................................131

• (DDRSS Switching Characteristics): Added a note that clarifies the min cycle time definition and references

the AM64x\AM243x DDR Board Design and Layout Guidelines.................................................................... 136

• (GPMC): Added IOSET information................................................................................................................143

• (GPMC and NOR Flash — Synchronous Mode): Added a note to Timing Requirements and Switching

Characteristics tables to clarify maximum frequency relationship to data bus width...................................... 143

• (System Power Supply Monitor Design Guidelines): Updated maximum and minumum threshold values to

remove a few mV of rounding error in example provided............................................................................... 224

• (Standard Package Symbolization): Updated package symbolization figure................................................. 227

• (Device Naming Convention): Added K option to Device Speed Grades row to table. Added Q1 Automotive

Designator Row to table................................................................................................................................. 227

• (Tools and Software): Updated the supported development tools.................................................................. 228

• (Documentation Support) Updated/Changed the URL of the Silicon Errata reference...................................229

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AM2434, AM2432, AM2431

SPRSP65C – APRIL 2021 – REVISED MARCH 2022

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