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AM2434BSDFHIALVR Datasheet(PDF) 74 Page - Texas Instruments |
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AM2434BSDFHIALVR Datasheet(HTML) 74 Page - Texas Instruments |
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74 / 242 page  Table 6-42. GPMC0 Signal Descriptions (continued) Signal Name [1] ((2)) Signal Type [2] Description [3] ALV PIN [4] ALX PIN [4] GPMC0_AD27 IO GPMC Data 27 Input/Output in A/D non-multiplexed mode and additionally Address 28 Output in A/D multiplexed mode AA8 V5 GPMC0_AD28 IO GPMC Data 28 Input/Output in A/D non-multiplexed mode and additionally Address 29 Output in A/D multiplexed mode U9 W2 GPMC0_AD29 IO GPMC Data 29 Input/Output in A/D non-multiplexed mode and additionally Address 30 Output in A/D multiplexed mode W9 V6 GPMC0_AD30 IO GPMC Data 30 Input/Output in A/D non-multiplexed mode and additionally Address 31 Output in A/D multiplexed mode AA9 AA7 GPMC0_AD31 IO GPMC Data 31 Input/Output in A/D non-multiplexed mode and additionally Address 0 Output in A/D multiplexed mode Y9 Y7 GPMC0_BE0n_CLE O GPMC Lower-Byte Enable (active low) or Command Latch Enable P17 GPMC0_BE1n O GPMC Upper-Byte Enable (active low) T19 P21 GPMC0_BE2n O GPMC Upper-Byte Enable (active low) V9 W6 GPMC0_BE3n O GPMC Upper-Byte Enable (active low) AA14 AA14 GPMC0_CSn0 O GPMC Chip Select 0 (active low) R19 GPMC0_CSn1 O GPMC Chip Select 1 (active low) R20 GPMC0_CSn2 O GPMC Chip Select 2 (active low) P19 GPMC0_CSn3 O GPMC Chip Select 3 (active low) R21 GPMC0_WAIT0 I GPMC External Indication of Wait W19 GPMC0_WAIT1 I GPMC External Indication of Wait Y18 (1) The RXACTIVE bit of the CTRLMMR_PADCONFIG32 register must be set to 0x1 and the TX_DIS bit of the CTRLMMR_PADCONFIG32 register must be reset to 0x0 when GPMC0 is operating in synchronous mode. (2) The GPMC0 interface is not supported by the AM243x_ALX device package. See AM243x_ALX Package - Unsupported Interfaces and Signals for additional details. AM2434, AM2432, AM2431 SPRSP65C – APRIL 2021 – REVISED MARCH 2022 www.ti.com 74 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: AM2434 AM2432 AM2431 |
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