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WM8940CGEFL/V Datasheet(PDF) 38 Page - Cirrus Logic |
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WM8940CGEFL/V Datasheet(HTML) 38 Page - Cirrus Logic |
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38 / 88 page  WM8940 38 Rev 4.4 Input Signal Output of PGA ALCLVL PGA Gain t HOLD Figure 16 ALC Hold Time ALCHLD tHOLD (s) 0000 0 0001 2.67ms 0010 5.34ms 0011 10.7ms 0100 21.4ms 0101 42.7ms 0110 85.4ms 0111 171ms 1000 342ms 1001 684ms 1010 1.37s Table 27 ALC Hold Time Values PEAK LIMITER To prevent clipping when a large signal occurs just after a period of quiet, the ALC circuit includes a limiter function. If the ADC input signal exceeds 87.5% of full scale ( –1.16dB), the PGA gain is ramped down at the maximum attack rate (as when ALCATK = 0000), until the signal level falls below 87.5% of full scale. This function is automatically enabled whenever the ALC is enabled. Note: If ALCATK = 0000, then the limiter makes no difference to the operation of the ALC. It is designed to prevent clipping when long attack times are used. |
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