WM8940CGEFLSLASHV datasheet(77/88 Pages) CIRRUS

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WM8940

Rev 4.4

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

REFER TO

5:0

PLLK[23:18]

001100

Fractional (K) part of PLL1 input/output frequency ratio

(treat as one 24-digit binary number).

Master Clock and

Phase Locked

Loop (PLL)

38 (26h)

15:9

00h

Reserved

8:0

PLLK[17:9]

010010011

Fractional (K) part of PLL1 input/output frequency ratio

(treat as one 24-digit binary number).

Master Clock and

Phase Locked

Loop (PLL)

39 (27h)

15:9

00h

Reserved

8:0

PLLK[8:0]

011101001

Fractional (K) part of PLL1 input/output frequency ratio

(treat as one 24-digit binary number).

Master Clock and

Phase Locked

Loop (PLL)

40 (28h)

15:0

0000h

Reserved

41 (29h)

15:0

0000h

Reserved

42 (2Ah)

15:2

Reserved

ALCZC

0 (zero

cross off)

ALC uses zero cross detection circuit.

0 = Disabled (recommended)

1 = Enabled

ALC Control 4

Reserved

43 (2Bh)

15:0

0000h

Reserved

44 (2Ch)

15:9

00h

Reserved

MBVSEL

Microphone Bias Voltage Control

0 = 0.9 * AVDD

1 = 0.75 * AVDD

Input Signal Path

7:4

Reserved

AUXMODE

Auxiliary Input Mode

0 = inverting buffer

1 = mixer (on-chip input resistor bypassed)

Input Signal Path

AUX2INPPGA

Select AUX amplifier output as input PGA signal

source.

0=AUX not connected to input PGA

1=AUX connected to input PGA amplifier negative

terminal.

Input Signal Path

MICN2INPPGA

Connect MICN to input PGA negative terminal.

0=MICN not connected to input PGA

1=MICN connected to input PGA amplifier negative

terminal.

Input Signal Path

MICP2INPPGA

Connect input PGA amplifier positive terminal to MICP

or VMID.

0 = input PGA amplifier positive terminal connected to

VMID

1 = input PGA amplifier positive terminal connected to

MICP through variable resistor string

Input Signal Path

45 (2Dh)

15:8

00h

Reserved

INPPGAZC

Input PGA zero cross enable:

0=Update gain when gain register changes

1=Update gain on 1st zero cross after gain register

write.

Input Signal Path

INPPGAMUTE

Mute control for input PGA:

0=Input PGA not muted, normal operation

1=Input PGA muted (and disconnected from the

following input BOOST stage).

Input Signal Path

WM8940CGEFL/V Datasheet(PDF) 77 Page - Cirrus Logic

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