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WM8940CGEFL/V Datasheet(PDF) 15 Page - Cirrus Logic |
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WM8940CGEFL/V Datasheet(HTML) 15 Page - Cirrus Logic |
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15 / 88 page ![]() WM8940 Rev 4.4 15 AUDIO INTERFACE TIMING – MASTER MODE BCLK (Output) ADCDAT FRAME (Output) t DL DACDAT t DDA t DHT t DST Figure 2 Digital Audio Data Timing – Master Mode (see Control Interface) Test Conditions DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, TA=+25 oC, Slave Mode, fs=48kHz, MCLK=256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT Audio Data Input Timing Information FRAME propagation delay from BCLK falling edge tDL 10 ns ADCDAT propagation delay from BCLK falling edge tDDA 15 ns DACDAT setup time to BCLK rising edge tDST 10 ns DACDAT hold time from BCLK rising edge tDHT 10 ns |
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