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WM8940CGEFL/V Datasheet(PDF) 14 Page - Cirrus Logic

Part # WM8940CGEFL/V
Description  Mono CODEC with Speaker Driver
PDF  88 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

WM8940CGEFL/V Datasheet(HTML) 14 Page - Cirrus Logic

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WM8940
14
Rev 4.4
SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCK TIMING
MCLK
t
MCLKL
t
MCLKH
t
MCLKY
Figure 1 System Clock Timing Requirements
Test Conditions
DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, TA = +25
oC
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNIT
System Clock Timing Information
MCLK cycle time
TMCLKY
MCLK=SYSCLK (=256fs)
81.38
ns
MCLK input to PLL Note 1
20
ns
MCLK duty cycle
TMCLKDS
60:40
40:60
Note 1:
PLL pre-scaling and PLL N and K values should be set appropriately so that SYSCLK is no greater than 12.288MHz.



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