WM8940CGEFLSLASHV datasheet(62/88 Pages) CIRRUS

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WM8940

Rev 4.4

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

GPIO

control

MODE_GPIO

Selects MODE as a GPIO pin

0 = MODE is an input. MODE selects 2-

wire mode when low and 3-wire mode

when high.

1 = MODE can be an input or output

under the control of the GPIO control

regardless of what happens on the MODE

pin.

Table 54 Mode is GPIO Control

Auto-incremental writes are supported in 2 wire and 3 wire modes. This is enabled by default.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

Control

Interface

AUTOINC

Auto-Incremental write enable

0=Auto-Incremental writes disabled

1=Auto-Incremental writes enabled

Table 55 Control Interface

3-WIRE SERIAL CONTROL MODE

In 3-wire mode, every rising edge of SCLK clocks in one data bit from the SDIN pin. A rising edge on

CSB/GPIO latches in a complete control word consisting of the last 16 bits.

B23

B20

B19

B18

B17

B16

B15

B14

B13

SDIN

SCLK

CSB

control register address

control register data bits

latch

B21

B22

Figure 34 3-Wire Serial Control Interface

READBACK IN 3-WIRE MODE

The following two timing diagrams are also supported.

Figure 35 Alternative 3-Wire Serial Control Timing

WM8940CGEFL/V Datasheet(PDF) 62 Page - Cirrus Logic

WM8940CGEFL/V Datasheet(HTML) 62 Page - Cirrus Logic

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