WM8940CGEFLSLASHV datasheet(66/88 Pages) CIRRUS

66 / 88 page

WM8940

Rev 4.4

POWER MANAGEMENT

VMID

The analogue circuitry will not work when VMID is disabled (VMIDSEL[1:0] = 00b). The impedance of

the VMID resistor string, together with the decoupling capacitor on the VMID pin will determine the

start-up time of the VMID circuit.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

Power

management 1

1:0

VMIDSEL

Reference string impedance to VMID pin

(determines startup time):

00=off (open circuit)

01=50k

Ω

10=250k

Ω

11=5k

Ω (for fastest startup)

Table 57 VMID Impedance Control

BIASEN

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

Power

management 1

BIASEN

Analogue amplifier bias control

0=Disabled

1=Enabled

Table 58 BIASEN Control

ESTIMATED SUPPLY CURRENTS

When either the DAC or ADC are enabled it is estimated that approximately 4mA will be drawn from

DCVDD when fs=48kHz (This will be lower at lower sample rates). When the PLL is enabled an

additional 700 microamps will be drawn from DCVDD.

Table 59 shows the estimated 3.3V AVDD current drawn by various circuits, by register bit.

AVDD CURRENT (MILLIAMPS)

MONOEN

0.2mA

PLLEN

1.4mA (with clocks applied)

MICBEN

0.5mA

BIASEN

0.3mA

BUFIOEN

0.1mA

VMIDSEL

10K=>0.3mA, less than 0.1mA for 100k/500k

BOOSTEN

0.2mA

INPPGAEN

0.2mA

ADCEN

2.6mA

MONOEN

0.2mA

SPKPEN

1mA from SPKVDD

SPKNEN

1mA from SPKVDD

MONOMIXEN

0.2mA

SPKMIXEN

0.2mA

DACEN

1.8mA

Table 59 AVDD Supply Current

WM8940CGEFL/V Datasheet(PDF) 66 Page - Cirrus Logic

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