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HT49CV7 Datasheet(PDF) 28 Page - Holtek Semiconductor Inc

Part # HT49CV7
Description  A/D With VFD Type 8-Bit MCU
PDF  48 Pages
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Manufacturer  HOLTEK [Holtek Semiconductor Inc]
Direct Link  http://www.holtek.com
Logo HOLTEK - Holtek Semiconductor Inc

HT49CV7 Datasheet(HTML) 28 Page - Holtek Semiconductor Inc

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HT49RV7/HT49CV7
Rev. 1.00
28
April 20, 2006
VFD Display Memory
The HT49RV7/HT49CV7 provides an area of embed-
ded data memory for the VFD display. This area is lo-
cated from 40H to 55H of the RAM at Bank 1. The Bank
Pointer (BP; located at 04H of the RAM) is the switch for
the RAM and the VFD display memory. When the BP is
set as
²1², any data written into 40H~55H will affect the
VFD display. When the BP is written as
²0², ²2², ²3² or
²4² any data written into 40H~55H is meant to access
the general purpose data memory. The VFD display
memory can be read and written to only by an indirect
addressing mode using MP1. When data is written into
the display data area, it is automatically read by the VFD
driver which then generates the corresponding VFD
driving signals. To turn the display on or off, a
²1² or a
²0² is written to the corresponding bit of the display
memory, respectively. The figure illustrates the mapping
between the display memory and VFD pattern for the
HT49RV7/HT49CV7.
7 6 t A D
A / D c o n v e r s i o n t i m e
7 6 t A D
A / D c o n v e r s i o n t i m e
0 0 0 B
0 0 0 B
1 0 0 B
0 1 0 B
0 0 0 B
S T A R T
E O C B
P C R 2 ~ P C R 0
A C S 2 ~ A C S 0
P o w e r - o n
R e s e t
E n d o f A / D
c o n v e r s i o n
1 : D e f i n e P B c o n f i g u r a t i o n
2 : S e l e c t a n a l o g c h a n n e l
1 . P B p o r t s e t u p a s I / O s
2 . A / D c o n v e r t e r i s p o w e r e d o f f
t o r e d u c e p o w e r c o n s u m p t i o n
A / D c l o c k m u s t b e f S Y S / 2 , f S Y S / 8 o r f S Y S / 3 2
N o t e :
S t a r t o f A / D
c o n v e r s i o n
R e s e t A / D
c o n v e r t e r
1 0 0 B
0 0 0 B
S t a r t o f A / D
c o n v e r s i o n
R e s e t A / D
c o n v e r t e r
A / D s a m p l i n g t i m e
3 2 t A D
M i n i m u m o n e i n s t r u c t i o n c y c l e n e e d e d
d o n ' t c a r e
A / D s a m p l i n g t i m e
3 2 t A D
E n d o f A / D
c o n v e r s i o n
A/D Conversion Timing
SEG15~SEG12
SEG11~SEG8
SEG7~SEG4
SEG3~SEG0
Grid0
41HU
41HL
40HU
40HL
Grid1
43HU
43HL
42HU
42HL
Grid2
45HU
45HL
44HU
44HL
Grid3
47HU
47HL
46HU
46HL
Grid4
49HU
49HL
48HU
48HL
Grid5
4BHU
4BHL
4AHU
4AHL
Grid6
4DHU
4DHL
4CHU
4CHL
Grid7
4FHU
4FHL
4EHU
4EHL
Grid8
51HU
51HL
50HU
50HL
Grid9
53HU
53HL
52HU
52HL
Grid10
55HU
55HL
54HU
54HL
VFD Display Memory



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