until the origin cause is removed and a new register reading operation is performed by the microprocessor. The

FLT pin must be connected to a positive voltage (5 V max.) by a pull-up resistor.

2.11

VMON: output voltage diagnostic

output voltage level is below the guaranteed limits, the relevant VMON I²C bit is set to “1”, see Table 16. Output

voltage diagnostic (VMON-A/B bits, STATUS 1 register) characteristics for more details.

2.12

TMON: 22 kHz tone diagnostic

The 22 kHz tone can be internally detected and monitored if one (or both) DETIN pin are connected to the LNB

output bus (see Figure 7. DiSEqC 2.x application circuit) through a decoupling capacitor.

The tone diagnostic function is provided with the corresponding TMON I²C bit. If the 22 kHz tone amplitude and/or

the tone frequency is out of the guaranteed limits, see Table 18. 22 kHz tone diagnostic (TMON-A/B bit, STATUS

2 register) characteristics, the corresponding TMON I²C bit is set to “1”.

2.13

TDET: 22 kHz tone detection

When a 22 kHz tone presence is detected on one DETIN pin, the corresponding TDET I²C bit is set to “1”.

2.14

IMON: minimum output current diagnostic

In order to detect the output load absence (no LNB connected on the bus or cable not connected to the IRD) each

LNBH26S section is provided with a minimum output current flag by the corresponding IMON I²C bit, accessible in

read mode, which is set to “1” if the output current is lower than 12 mA (typ.). It is recommended to use the IMON

function only with the 22 kHz tone transmission deactivated, otherwise the IMON bit could be set to “0” even if the

output current is below the minimum current threshold. To activate the IMON diagnostic function, set to “1” the

EN_IMON I²C bit in the DATA4 register. Be aware that as soon as the IMON function is activated by means of

operation is applied in order to be sure that the LNBH26S output has the higher voltage present in the LNB bus.

Do not use this function in an application environment where a 21 V voltage level is not supported by other

peripherals connected to the LNB bus.

2.15

PDO: overcurrent detection on output pull-down stage

When an overcurrent occurs on one section pull-down output stage due to an external voltage source greater

For current threshold and deglitch time details, see Table 12. A/B section electrical characteristics.

2.16

Power-on I²C interface reset and undervoltage lockout

undervoltage lockout (UVLO) threshold (4.7 V typ.), the interface does not respond to any I²C command and all

DATA register bits are initialized to zeroes, therefore keeping the power blocks disabled. Once the VCC rises

above 4.8 V typ., the I²C interface becomes operative and the DATA registers can be configured by the main

microprocessor.

2.17

PNG: input voltage minimum detection

set to “1” and the FLT pin is set LOW.

LNBH26S

VMON: output voltage diagnostic

DS8975 - Rev 5

page 6/35