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LNBH26S Datasheet(PDF) 4 Page - STMicroelectronics

Part # LNBH26S
Description  Dual LNBS supply and control I2C with step-up and IC interface
PDF  35 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

LNBH26S Datasheet(HTML) 4 Page - STMicroelectronics

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2.3
Data encoding by external DiSEqC envelope control through the DSQIN pin
If an external DiSEqC™ envelope source is available, it is possible to use the internal 22 kHz generator activated
during the tone transmission by connecting the DiSEqC™ envelope source to the DSQIN pin. In this case the I²C
tone control bits must be set: EXTM=0 and TEN=1. In this way the internal 22 kHz signal is superimposed on the
VOUT DC voltage to generate the LNB output 22 kHz tone. During the period in which the DSQIN is kept HIGH the
internal control circuit activates the 22 kHz tone output.
The 22 kHz tone on the VOUT pin is activated with a delay of about 6 µs from DSQIN TTL signal rising edge, and
it stops with a delay time in the range of 15 µs to 60 µs after the 22 kHz TTL signal on DSQIN has expired, refer
to Figure 3. Tone enable and disable timing (using envelope signal).
Figure 3. Tone enable and disable timing (using envelope signal)
~ 6 µs
15 µs ~ 60 µs
DSQIN
Tone
output
GIPG2601151226LM
2.4
LPM (low power mode)
In order to reduce total power loss, each section of the LNBH26S is provided with the LPM I²C bit that can be
activated (LPM=1) in applications where the 22 kHz tone can be disabled for long time periods. The LPM bit can
be set to “1” when the DiSEqC™ data transmission is not requested (no 22 kHz tone output is present); in this
condition the drop voltage across the integrated LDO regulator (VUP - VOUT) is reduced to 0.6 V typ. and,
consequently, the power loss inside the relative LNBH26S channel regulator is reduced too. For example, at 500
mA load, LPM=1, allowing a minimum LDO dissipated power of 0.3 W typ. It is recommended to set the LPM bit
to “0” before starting the 22 kHz DiSEqC™ data transmission; in this condition the drop voltage across the LDO is
kept to 1 V typ. Keep LPM=0 all times if LPM function is not used.
2.5
DISEQC™ 2.0 implementation
The built-in 22 kHz tone detector completes the fully bi-directional DiSEqC™ 2.0 interfacing. Each LNBH26S
section DETIN pin must be AC coupled to the DiSEqC™ bus, and extracted PWK data is available on the
corresponding DSQOUT pin. To comply with the bi-directional DiSEqC™ 2.0 bus hardware requirements, an
output R-L filter is needed (per each voltage output pin). In order to avoid 22 kHz waveform distortion during tone
transmission, each LNBH26S section is provided with a BPSW pin to be connected to an external transistor,
which allows the bypassing of the corresponding output RL filter in DiSEqC 2.x applications while in transmission
mode. Before starting tone transmission by means of the DSQIN pin, provide that the TEN bit is preventively set
to “1” and after ending tone transmission, provide that the TEN bit is set to “0”.
2.6
Output current limit selection
The linear regulators current limit threshold can be set by an external resistor connected to the ISEL pin. The
resistor value defines the output current limit by the equation:
IMAXtyp. = 16578
RSEL1.206
(1)
with ISET = 0
IMAXtyp. = 6452
RSEL1.159
(2)
with ISET = 1
LNBH26S
Data encoding by external DiSEqC envelope control through the DSQIN pin
DS8975 - Rev 5
page 4/35



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