LNBH26S datasheet(8/35 Pages) STMICROELECTRONICS

8 / 35 page

Pin configuration

Figure 5. Pin connections (top view)

GND

DSQOUT-A

DSQIN-B

DSQIN-A

VUP-A

VCC

PGND

FLT

LX-B

LX-A

SDA

ISEL

VOUT-B

DETIN-A

VUP-B

BPSW-B

VOUT-A

DSQOUT-B

BYP

BPSW-A

ADDR

DETIN-B

SCL

GIPG2701151333LM

Table 1. Pin description

Symbol

Name

Pin function

DSQOUT-B

DiSEqC output

Open drain output of channel A tone detector to the main microcontroller for

DiSEqC 2.0 data decoding. It is low when tone is detected on the DETIN-B input

pin. Set to ground if not used.

FLT

Open drain output for IC fault conditions. It is set low in case of overload (OLF bit)

or overheating status (OTF bit) or power not good (PNG bit) is detected. To be

connected to pull-up resistor (5 V max.).

LX-A

NMOS drain

Channel A, integrated N-channel power MOSFET drain.

P-GND

Power ground

DC-DC converter power ground. To be connected directly to the exposed pad.

LX-B

NMOS drain

Channel B, integrated N-channel power MOSFET drain.

ADDR

Address setting

Two I2C bus addresses available by setting the address pin level voltage. See

Table 15. Address pin characteristics.

SCL

Serial clock

Clock from I²C bus.

SDA

Serial data

Bi-directional data from/to I²C bus.

ISEL

Current selection

for both channel A

and B

The resistor “RSEL” connected between ISEL and GND defines the linear

regulator current limit threshold. Refer to Section 2.5 DISEQC™ 2.0

implementation. The RSEL resistor defines the same current limit both for

channels A and B.

N.C.

Not internally

connected

Not internally connected pin. Set floating if not used.

LNBH26S

Pin configuration

DS8975 - Rev 5

page 8/35

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