L9966 datasheet(51/122 Pages) STMICROELECTRONICS

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SPI interface

For SPI communication an in-frame protocol is used. This means the complete SPI transmission is finished within

one CS low phase. The requested data is transmitted to the master in the same SPI frame. Furthermore, the SPI

interface offers a burst feature for read and write commands.

The SPI interface is designed to work up to a clock frequency (SCLK) of 10 MHz

13.1

SPI interface characteristics

During active reset conditions the SPI is driven into its default state. When reset becomes inactive, the state

machine enters into a wait state for the next instruction. During active reset conditions the output MISO is

high impedance (HiZ).

If the signal at CS is inactive (high), the state machine is forced to enter the wait state waiting for

instructions. CS is kept inactive when RST is active low.

During active (low) state of the CS, the falling edge of the serial clock signal SCLK is used to latch the input

data at MOSI (this corresponds to MCU SPI peripheral configuration CPOL=0; CPHA=1). Output data at

MISO is driven with the rising edge of SCLK. Further processing of the data according to the instruction (i.e.

modification of internal registers) is triggered by the rising edge of the CS signal.

Chip address: In order to support two L9966 working on a fully shared SPI bus, each frame has to contain

the chip address, reported on the two MSB of each instruction byte. To avoid a bus conflict the output MISO

remains at HiZ during the addressing phase of the frame: if the chip address does not match, the frame is

ignored and MISO remains HiZ, even in case the instruction bit should match a valid instruction. A frame

with not matching chip address is ignored and does not generate any Transfer Failure Message.

Check byte: Simultaneously to the receipt of an SPI instruction the FlexInput transmits a check byte via the

output MISO to the controller. This byte indicates regular or irregular operation of the SPI. It contains an

initial fixed bit pattern and a flag indicating an eventual invalid instruction of the previous access.

On a read access the data bit at the SPI input MOSI are rejected/ignored, but parity check is always

performed.

Invalid access. An access is invalid, if one of the following conditions are fulfilled:

–

An unused/invalid instruction code is detected. An instruction code is not valid when its address doesn’t

exist.

–

In case the previous transmission was not completed (CS went inactive too early)

–

The parity bit of either MOSI instruction (PAR_MOSI_INST) or MOSI data (PAR_MOSI_DATA) frame is

wrong.

If an invalid instruction is detected, no modifications on registers of the FlexInput will be performed. In case

an unused instruction code occurred, the expected answer is collected with PAR_MISO_DATA = ‘1’ and all

data bit at 1; the resulting word, transmitted after having sent the check byte, is then 0xFFFF.

In order to guarantee SPI proper operation, CS signal must remain de-asserted for at least tSPICS-high in

between two consecutive SPI accesses. During this time, the eventual SPI configuration/command becomes

effective and the L9966 gets ready for a new SPI exchange.

A write access is internally suppressed (i.e. internal registers will not be affected) in all cases where the number of

falling edges of SCLK applied to the SPI input is not equal to 32 at the rising (inactive) edge of CS (respectively

16*(m+1) clock pulses in burst mode, where m indicates the burst packets sent).

For each of the invalid access types reported above, a Transfer Failure bit (TRANS_F) is set and can be read on

MISO at next SPI transaction. On top of all the cases reported above, de-assertion of RST with CS asserted (low)

determines the setting of TRANS_F bit in first SPI frame.

In Figure 26. Write access (32 bits frame) and Figure 27. Read access (32 bits frame) are reported SPI frame

examples:

L9966

SPI interface

DS12459 - Rev 10

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