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L9966 Datasheet(PDF) 69 Page - STMicroelectronics |
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L9966 Datasheet(HTML) 69 Page - STMicroelectronics |
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69 / 122 page ![]() Once a new value is defined, new hysteresis threshold is applied after the second VRS_OUT HL transition and until the next rising edge of the VRS input differential voltage occurs. 15.2.6 VRS_B –Limited Adaptive Hysteresis To set the limited adaptive hysteresis on VRS_B configuration, bit VRS_CONF_MODE[0] has to be set to ‘1’. In this mode, user programs a hysteresis threshold through VRS_HYST_CONF[2:0] bit in VRS register and the internal logic selects a hysteresis based on input signal peak value (see Section 15.2.3 VRS_A – Fully adaptive hysteresis): the maximum of these two values is actually applied. Default hysteresis current after exiting reset is HI1. Once a new value is defined, new hysteresis threshold is applied after the first or the second VRS_OUT HL transition depending on LIM_ADAP_DOUBLE_EDGE bit in VRS register, if the bit has been fixed “0” the new hysteresis value is applied after the first VRS_OUT HL transition (default), otherwise after the second. Current hysteresis value is active until the next rising edge of the VRS input differential voltage occurs. When VRS_B architecture is selected, it is possible to force the hysteresis current to its minimum value through HYST_MIN_FORCE of VRS register regardless of the content of VRS_HYST_CONF [1,0] bit. Default hysteresis current after exiting reset is HI1. 15.2.7 VRS_B – Fixed Filter Time In VRS_B configuration, it is possible to enable the filter time on the output of the zero crossing comparator through the bit VRS_CONF_MODE[1] of VRS register. This configuration allows defining the internal filter time at a fixed value of 2.5 µs, active on both rising and falling edges of VRS output. The starting filter time period at power on reset is 125 µs. As per VRS_A architecture, VRS_FE_FLT_EN allows configuring the same two different strategies for the filtering algorithm (see Section 15.2.4 VRS_A – Adaptive Filter Time). 15.3 VRS Diagnostic Mode The diagnostic mode is selected through VRS_EN_DIAG = ‘1’ in VRS register. This mode provides feedback to detect faulty conditions either on VRSP or VRSN. To be noted that diagnostic results are not reliable while the flying wheel is rotating. If a fault is detected in DIAG mode, VRS correct functionality is not guaranteed. Based on three comparators, it is possible to detect an open load fault condition, a short to ground or a short to battery fault condition. Fault bit VRS_FAULT[1:0] of VRS register are consequently set. Once a fault has been detected being the diagnostic active (VRS_EN_DIAG=1) if the faulty condition is stable, DIAG_CLEAR_CMD set does not clear VRS_FAULT[1:0] field; if the faulty condition is solved, a write SPI access with DIAG_CLEAR_CMD=1 clears VRS_FAULT[1:0] field in terms of internal device register; only through another SPI access (either write or read access) determines VRS_FAULT[1:0] reset in SPI VRS register. Once a fault has been detected (VRS_EN_DIAG=1), the reset of VRS_FAULT[1:0] field because of the diagnostic has been switched off, requires three SPI accesses: • The first one to switch off the diagnostic and any DIAG_CLEAR_CMD set in the same frame is ignored • Once the diagnostic is switched off, DIAG_CLEAR_CMD set determines the reset of VRS_FAULT[1:0] field in the internal register; • The next SPI access (W or R) shows on SPI that VRS_FAULT[1:0] field in VRS register has been cleared Figure 38. VRS block diagram - Diagnostic operating mode - Current path shows the circuit used in Diagnostic mode. When VRS diagnostic mode is activated, VRSP is fixed at Vcm_DIAG and IDIAG current generator is enabled ; the current path is the one in yellow in Figure 38. VRS block diagram - Diagnostic operating mode - Current path. L9966 VRS Diagnostic Mode DS12459 - Rev 10 page 69/122 |
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