CS42L92 datasheet(39/333 Pages) CIRRUS

39 / 333 page

DS1162F2

CS42L92

4.2 Input Signal Path

R792 (0x0318)

IN2L_Control

IN2L_HPF

Input Path 2 (Left) HPF Enable

0 = Disabled

1 = Enabled

12:11 IN2_DMIC_

SUP[1:0]

Input Path 2 DMIC Reference Select (sets the DMICDAT2 and DMICCLK2 logic levels)

00 = MICVDD

01 = MICBIAS1

10 = MICBIAS2

11 = Reserved

IN2_MODE

Input Path 2 Mode

0 = Analog input

1 = Digital input

7:1 IN2L_PGA_

VOL[6:0]

0x40 Input Path 2 (Left) PGA Volume (applicable to analog input only)

0x00 to 0x3F = Reserved

0x40 = 0 dB

0x41 = 1 dB

0x42 = 2 dB

… (1-dB steps)

0x5F = 31 dB

0x60 to 0x7F = Reserved

R793 (0x0319)

ADC_Digital_

Volume_2L

14:13 IN2L_

SRC[1:0]

Input Path 2 (Left) Source

00 = Differential (IN2ALP–IN2ALN)

01 = Single-ended (IN2ALP)

10 = Differential (IN2BL–IN2ALN)

11 = Single-ended (IN2BL)

IN2L_LP_

MODE

Input Path 2 (Left) Low-Power Mode (applicable to analog input only)

0 = High Performance Mode

1 = Low Power Mode

R794 (0x031A)

DMIC2L_Control

10:8 IN2_

OSR[2:0]

101

Input Path 2 Oversample Rate Control

If analog input is selected, this field is used to select Mid-Power Mode.

100 = Mid Power Mode

101 = Normal

All other codes are reserved

If digital input is selected, this field controls the DMICCLK2 frequency.

010 = 384 kHz

011 = 768 kHz

100 = 1.536 MHz

101 = 3.072 MHz

110 = 6.144 MHz

All other codes are reserved

R796 (0x031C)

IN2R_Control

IN2R_HPF

Input Path 2 (Right) HPF Enable

0 = Disabled

1 = Enabled

7:1 IN2R_PGA_

VOL[6:0]

0x40 Input Path 2 (Right) PGA Volume (applicable to analog input only)

0x00 to 0x3F = Reserved

0x40 = 0 dB

0x41 = 1 dB

0x42 = 2 dB

… (1-dB steps)

0x5F = 31 dB

0x60 to 0x7F = Reserved

R797 (0x0319)

ADC_Digital_

Volume_2R

14:13 IN2R_

SRC[1:0]

Input Path 2 (Right) Source

00 = Differential (IN2ARP–IN2ARN)

01 = Single-ended (IN2ARP)

10 = Differential (IN2BR–IN2ARN)

11 = Single-ended (IN2BR)

IN2R_LP_

MODE

Input Path 2 (Right) Low-Power Mode (applicable to analog input only)

0 = High Performance Mode

1 = Low Power Mode

R800 (0x0320)

IN3L_Control

IN3L_HPF

Input Path 3 (Left) HPF Enable

0 = Disabled

1 = Enabled

12:11 IN3_DMIC_

SUP[1:0]

Input Path 3 DMIC Reference Select (sets the DMICDAT3 and DMICCLK3 logic levels)

00 = MICVDD

01 = MICBIAS1

10 = MICBIAS2

11 = Reserved

R802 (0x0322)

DMIC3L_Control

10:8 IN3_

OSR[2:0]

101

Input Path 3 Oversample Rate Control - selects the DMICCLK3 frequency.

010 = 384 kHz

011 = 768 kHz

100 = 1.536 MHz

101 = 3.072 MHz

110 = 6.144 MHz

All other codes are reserved

R804 (0x0324)

IN3R_Control

IN3R_HPF

Input Path 3 (Right) HPF Enable

0 = Disabled

1 = Enabled

Table 4-3. Input Signal Path Configuration (Cont.)

Bit

Label

Default

Description

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