CS42L92 datasheet(37/333 Pages) CIRRUS

37 / 333 page

DS1162F2

CS42L92

4.2 Input Signal Path

4.2.5

Input Signal Path Sample-Rate Control

The input signal paths may be selected as input to the digital mixers or signal-processing functions within the CS42L92

digital core. The sample rate for the input signal paths can be set globally, or can be configured independently for each

input channel.

The IN_RATE_MODE bit (defined in Table 4-3) controls whether the input sample rates are set globally using IN_RATE,

or independently for each input channel using the INnx_RATE fields (where n is 1–4 and x is L or R for the left/right

channels respectively). The IN_RATE and INnx_RATE fields are defined in Table 4-26.

Note that sample-rate conversion is required when routing the input signal paths to any signal chain that is asynchronous

or configured for a different sample rate.

4.2.6

Input Signal Path Configuration

The CS42L92 supports up to eight analog inputs or up to eight digital inputs. Selectable combinations of analog (mic or

line) and digital inputs are multiplexed into four stereo input signal paths.

Input paths IN1 and IN2 can be configured for single-ended, differential, or DMIC operation. The analog input configuration

and pin selection is controlled using the INnx_SRC bits; digital input mode is selected by setting INn_MODE.

Input paths IN3 and IN4 support digital inputs only. Note that the external pin connections are shared with the IN1R and

IN2R analog input paths—the following restrictions apply:

• If IN3L or IN3R input paths are enabled, IN1R analog input is restricted to differential (IN1BR–IN1ALN) or

single-ended (IN1BR) configurations only.

• If IN4L or IN4R input paths are enabled, IN2R analog input is restricted to single-ended (IN2BR) configuration only.

A configurable high-pass filter (HPF) is provided on the left and right channels of each input path. The applicable cut-off

frequency is selected using IN_HPF_CUT. The filter can be enabled on each path independently using the INnx_HPF bits.

The analog input signal paths (single-ended or differential) each incorporate a PGA to provide gain in the range 0 dB to

+31 dB in 1-dB steps. Note that these PGAs do not provide pop suppression functions; it is recommended that the gain

should not be adjusted while the respective signal path is enabled.

The analog input PGA gain is controlled using INnL_PGA_VOL and INnR_PGA_VOL. Note that separate volume control

is provided for the left and right channels of each stereo pair.

If DMIC input is selected, the respective DMICCLKn frequency is controlled by the respective INn_OSR field.

If a signal path is configured for DMIC input, the voltage reference for the associated input/output pins is selectable using

the INn_DMIC_SUP fields—each interface may be referenced to MICVDD, MICBIAS1, or MICBIAS2. The voltage

reference for each digital input path should be set equal to the applicable power supply of the respective microphones.

The CS42L92 input paths can be configured for power-saving operation, ideal for always-on applications. The low-power

configurations allow the power consumption to be optimized with respect to the required audio performance

characteristics.

• If a signal path is configured for analog input, low-power operation can be selected by setting the respective INnx_

LP_MODE bit. Mid-power operation can be configured by setting INn_OSR = 100 for the respective signal paths.

(Note that the INnx_LP_MODE bit should be cleared in the mid-power configuration.) Note that the maximum

input-signal level is reduced by 6 dB if mid-power operation is selected—see Table 3-4.

• If a signal path is configured for digital input, the respective DMICCLKn frequency can be configured using the INn_

OSR bits. Reducing the DMICCLKn frequency reduces power consumption at the expense of audio performance.

The INn_OSR field also supports high performance DMIC mode, when 6.144 MHz DMICCLK is selected.

If 384- or 768-kHz DMICCLKn frequency is selected, the maximum sample rate for the respective paths is restricted

as described in Table 4-1. If the input sample rates are set globally using IN_RATE (i.e., IN_RATE_MODE = 0), all

input paths are affected similarly.

The MICVDD voltage is generated by an internal charge pump and LDO regulator. The MICBIASn outputs are derived

from MICVDD; see Section 4.19.

CS42L92 Datasheet(PDF) 37 Page - Cirrus Logic

CS42L92 Datasheet(HTML) 37 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL