CS42L92 datasheet(68/333 Pages) CIRRUS

68 / 333 page

DS1162F2

CS42L92

4.3 Digital Core

Figure 4-23. Digital-Core LPF/HPF Blocks

The LHPF1–LHPF4 mixer control fields, shown in Fig. 4-23, are located at register addresses R2304–R2335

(0x0900–0x091F).

The full list of digital mixer control registers (R1600–R3576) is provided in Section 6. Generic register field definitions are

provided in Table 4-11.

The x_SRCn fields select the input sources for the respective LHPF processing blocks. Note that the selected input

sources must be configured for the same sample rate as the LHPF to which they are connected. Sample-rate conversion

functions are available to support flexible interconnectivity; see Section 4.3.15 and Section 4.3.16.

The hexadecimal numbers in Fig. 4-23 indicate the corresponding x_SRCn setting for selection of that signal as an input

to another digital-core function.

The sample rate for the LHPF function is configured using FX_RATE; see Table 4-26. Note that the EQ, DRC, and LHPF

functions must all be configured for the same sample rate. Sample-rate conversion is required when routing the LHPF

signal paths to any signal chain that is asynchronous or configured for a different sample rate.

The FX_RATE field must not be changed if any of the associated x_SRCn fields is nonzero. The associated x_SRCn fields

must be cleared before writing a new value to FX_RATE. A minimum delay of 125

s must be allowed between clearing

the x_SRCn fields and writing to FX_RATE. See Table 4-26 for details.

The control registers associated with the LHPF functions are described in Table 4-19.

The cut-off frequencies for the LHPF blocks are set by using the coefficients held in registers R3777, R3781, R3785, and

R3789 for LHPF1, LHPF2, LHPF3 and LHPF4 respectively. These coefficients are derived using tools provided in Cirrus

Logic’s WISCE evaluation board control software; please contact your Cirrus Logic representative for details.

Table 4-19. Low-Pass Filter/High-Pass Filter

Label

Default

Description

R3585 (0x0E01)

FX_Ctrl2

15:4 FX_STS[11:0]

0x00 LHPF, DRC, EQ Enable Status. Indicates the status of the respective

signal-processing functions. Each bit is coded as follows:

0 = Disabled

1 = Enabled

[11] = EQ4

[10] = EQ3

[9] = EQ2

[8] = EQ1

[7] = DRC2 (Right)

[6] = DRC2 (Left)

[5] = DRC1 (Right)

[4] = DRC1 (Left)

[3] = LHPF4

[2] = LHPF3

[1] = LHPF2

[0] = LHPF1

LHPFnMIX_SRC1

LHPFnMIX_SRC3

LHPFnMIX_SRC4

LHPFnMIX_SRC2

LHPF1 (0x60)

LHPF2 (0x61)

LHPF3 (0x62)

LHPF4 (0x63)

Low-Pass filter (LPF) /

High-Pass filter (HPF)

LHPFnMIX_VOL2

LHPFnMIX_VOL3

LHPFnMIX_VOL4

LHPFnMIX_VOL1

LHPF

…

CS42L92 supports four LHPF blocks, i.e., n = 1–4

x_SRCn p. 52

x_VOLn p. 52

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