CS47L35 datasheet(210/300 Pages) CIRRUS

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DS1085F3

CS47L35

4.18 Control-Write Sequencer

Fig. 4-73 shows a multiple register read from a specified address.

Figure 4-73. Multiple-Register Read from Specified Address

4.18 Control-Write Sequencer

The control-write sequencer is a programmable unit that forms part of the CS47L35 control interface logic. It provides the

ability to perform a sequence of register-write operations with the minimum of demands on the host processor—the

sequence may be initiated by a single operation from the host processor and then left to execute independently.

Default sequences for pop-suppressed start-up and shutdown of each headphone/earpiece output driver are provided

(these are scheduled automatically when the respective output paths are enabled or disabled). Other control sequences

can be programmed, and may be associated with sample-rate detection, DRC, MICDET clamp, or event-logger status;

these sequences are automatically scheduled whenever a corresponding event is detected.

When a sequence is initiated, the sequencer performs a series of predefined register writes. The start index of a control

sequence within the sequencer’s memory may be commanded directly by the host processor. The applicable start index

for each of the sequences associated with sample-rate detection, DRC, or MICDET clamp, or event logger status is held

in a user-programmed control register.

The control-write sequencer may be triggered by a number of different events. Multiple sequences are queued if

necessary, and each is scheduled in turn.

The control-write sequencer can be supported with or without system clocking—there is no requirement for SYSCLK or for

any other system clock to be enabled when using the control-write sequencer. The timing accuracy of the sequencer

operation is improved when SYSCLK is present, but the general functionality is supported with or without SYSCLK.

4.18.1 Initiating a Sequence

The fields associated with running the control-write sequencer are described in Table 4-102.

The CS47L35 provides 16 general-purpose trigger bits for the write sequencer to allow easy triggering of the associated

control sequences. Writing 1 to the trigger bit initiates a control sequence, starting at the respective index position within

the control-write sequencer memory.

The WSEQ_TRG1_INDEX field defines the sequencer start index corresponding to the WSEQ_TRG1 trigger control bit.

Equivalent start index fields are provided for each of the trigger control bits, as described in Table 4-102. Note that a

sequencer start index of 0x1FF causes the respective sequence to be aborted.

The general-purpose control sequences are undefined following power-on reset, a hardware reset, or a Sleep Mode

transition. The general-purpose control sequences must be reconfigured by the host processor following any of these

events. Note that all control sequences are maintained in the sequencer memory through software reset.

The write sequencer can also be commanded using control bits in register R22 (0x16). In this case, the write sequencer

is enabled using the WSEQ_ENA bit and the index location of the first command in the sequence is held in the WSEQ_

START_INDEX field. Writing 1 to the WSEQ_START bit commands the sequencer to execute a control sequence, starting

at the specified index position. Note that, if the sequencer is already running, the WSEQ_START command is queued and

executed when the sequencer becomes available.

Device ID

Address Byte [3]

(0)

Device ID

(1)

Read from Register Address

MSByte Data 0

LSByte Data 0

MSByte Data N

LSByte Data N

MSByte Data N-1

LSByte Data N-1

Read from Register Address+ N

Read from Register Address + N - 1

Address Byte [2]

Address Byte [1]

Address Byte [0]

R/W

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