CS47L35 datasheet(213/300 Pages) CIRRUS

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CS47L35

4.18 Control-Write Sequencer

As many as four audio sample rates can be configured for automatic detection; these sample rates are selected using the

SAMPLE_RATE_DETECT_n fields. If a selected audio sample rate is detected, the control-write sequencer is triggered.

The applicable start index location within the sequencer memory is separately configurable for each detected sample rate.

The WSEQ_SAMPLE_RATE_DETECT_A_INDEX field defines the sequencer start index corresponding to the SAMPLE_

RATE_DETECT_A sample rate. Equivalent start index fields are defined for the other sample rates, as described in

Table 4-103.

Note that a sequencer start index of 0x1FF causes the respective sequence to be aborted.

The automatic sample-rate detection control sequences are undefined following power-on reset, a hardware reset, or a

Sleep Mode transition. The automatic sample-rate detection control sequences must be reconfigured by the host

processor following any of these events. Note that all control sequences are maintained in the sequencer memory through

software reset.

See Section 4.16 for further details of the automatic sample-rate detection function.

4.18.3 DRC Signal-Detect Sequences

The DRC function within the CS47L35 digital core provides a configurable signal-detect function. This allows the signal

level at the DRC input to be monitored and used to trigger other events.

The DRC signal-detect functions are enabled and configured using the fields described in Table 4-13 and Table 4-14 for

DRC1 and DRC2 respectively.

A control-write sequence can be associated with a rising edge and/or a falling edge of the DRC1 signal-detect output. This

is enabled by setting DRC1_WSEQ_SIG_DET_ENA, as described in Table 4-13.

Note that signal detection is supported on DRC1 and DRC2, but the triggering of the control-write sequencer is available

on DRC1 only.

When the DRC signal-detect sequence is enabled, the control-write sequencer is triggered whenever the DRC1

signal-detect output transitions (high or low). The applicable start index location within the sequencer memory is separately

configurable for each logic condition.

The WSEQ_DRC1_SIG_DET_RISE_SEQ_INDEX field defines the sequencer start index corresponding to a DRC1

signal-detect rising edge event, as described in Table 4-104. The WSEQ_DRC1_SIG_DET_FALL_SEQ_INDEX field

defines the sequencer start index corresponding to a DRC1 signal-detect falling edge event.

Note that a sequencer start index of 0x1FF causes the respective sequence to be aborted.

The DRC signal-detect sequences cannot be independently enabled for rising and falling edges. Instead, a start index of

0x1FF can be used to disable the sequence for either edge, if required.

Table 4-103. Write Sequence Control—Automatic Sample-Rate Detection

Bit

Label

Default

Description

R97 (0x0061)

Sample_Rate_

Sequence_Select_1

8:0

WSEQ_SAMPLE_

RATE_DETECT_

A_INDEX[8:0]

0x1FF Sample Rate A Write Sequence start index. Contains the index location in the

sequencer memory of the first command in the sequence associated with Sample

Rate A detection.

Valid from 0 to 251 (0x0FB).

R98 (0x0062)

Sample_Rate_

Sequence_Select_2

8:0

WSEQ_SAMPLE_

RATE_DETECT_

B_INDEX[8:0]

0x1FF Sample Rate B Write Sequence start index. Contains the index location in the

sequencer memory of the first command in the sequence associated with Sample

Rate B detection.

Valid from 0 to 251 (0x0FB).

R99 (0x0063)

Sample_Rate_

Sequence_Select_3

8:0

WSEQ_SAMPLE_

RATE_DETECT_

C_INDEX[8:0]

0x1FF Sample Rate C Write Sequence start index. Contains the index location in the

sequencer memory of the first command in the sequence associated with Sample

Rate C detection.

Valid from 0 to 251 (0x0FB).

R100 (0x0064)

Sample_Rate_

Sequence_Select_4

8:0

WSEQ_SAMPLE_

RATE_DETECT_

D_INDEX[8:0]

0x1FF Sample Rate D Write Sequence start index. Contains the index location in the

sequencer memory of the first command in the sequence associated with Sample

Rate D detection.

Valid from 0 to 251 (0x0FB).

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