CS47L35 datasheet(217/300 Pages) CIRRUS

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CS47L35

4.18 Control-Write Sequencer

4.18.9 Sequencer Memory Definition

The write sequencer memory defines up to 252 write operations; these are indexed as 0 to 251 in the sequencer memory

map.

The write sequencer memory reverts to its default contents following power-on reset, a hardware reset, or a Sleep Mode

transition. In these cases, the sequence memory contains the boot sequence and the OUT1–OUT4 signal path enable/

disable sequences; the remainder of the sequence memory is undefined.

User-defined sequences can be programmed after power-up. The user-defined control sequences must be reconfigured

by the host processor following power-on reset, a hardware reset, or a Sleep Mode transition. Note that all control

sequences are maintained in the sequencer memory through software reset. See Section 5.2 for a summary of the

CS47L35 memory reset conditions.

The default control sequences can be overwritten in the sequencer memory, if required. Note that the headphone and

earpiece output path enable bits (HPnx_ENA, SPKOUTx_ENA) always trigger the write sequencer (at the predetermined

start index addresses).

Writing 1 to the WSEQ_LOAD_MEM bit clears the sequencer memory to the power-on reset state.

The sequencer memory is summarized in Table 4-111. User-defined sequences should be assigned space within the

allocated portion (user space) of the write sequencer memory.

The start index for the user-defined sequences is configured using the fields described in Table 4-102 through

Table 4-106.

Table 4-109. Write Sequencer Control—Programming a Sequence

Bit

Label

Default

Description

R12288 (0x3000)

WSEQ_

Sequence_1

31:29 WSEQ_DATA_

WIDTH0[2:0]

000

Width of the data block written in this sequence step.

000 = 1 bit

001 = 2 bits

010 = 3 bits

011 = 4 bits

100 = 5 bits

101 = 6 bits

110 = 7 bits

111 = 8 bits

WSEQ_MODE0

Extended Sequencer Instruction select

0 = Basic instruction set

1 = Extended instruction set

27:16 WSEQ_ADDR0[11:0] 0x000 Control Register Address to be written to in this sequence step.

The register address is calculated as: (Base Address * 512) + WSEQ_ADDRn.

Base Address is 0x00_0000 by default, and is configured using the sequencer’s

extended instruction set.

15:12 WSEQ_DELAY0[3:0]

0000 Time delay after executing this step.

0x0 = 3.3

s

0x1 to 0xE = 61.44

s x ((2WSEQ_DELAY)–1)

0xF = End of sequence marker

11:8 WSEQ_DATA_

START0[3:0]

0000 Bit position of the LSB of the data block written in this sequence step.

0000 = Bit 0

…

1111 = Bit 15

7:0 WSEQ_DATA0[7:0]

0x00 Data to be written in this sequence step. When the data width is less than 8 bits,

one or more of the MSBs of WSEQ_DATAn are ignored. It is recommended that

unused bits be cleared.

Table 4-110. Write Sequencer Control—Load Memory Control

Bit

Label

Default

Description

R24 (0x0018)

Write_Sequencer_Ctrl_2

WSEQ_LOAD_

MEM

Writing 1 to this bit resets the sequencer memory to the power-on reset

state.

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