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CS47L35 Datasheet(PDF) 216 Page - Cirrus Logic

Part # CS47L35
Description  Smart Codec with Low-Power Audio DSP
PDF  300 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS47L35 Datasheet(HTML) 216 Page - Cirrus Logic

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DS1085F3
CS47L35
4.18 Control-Write Sequencer
4.18.8 Programming a Sequence
A control-write sequence comprises a series of write operations to data bits within the control register map. Standard write
operations are defined by 5 fields, contained within a single 32-bit register. An extended instruction set is also defined; the
associated actions makes use of alternate definitions of the 32-bit registers.
The sequencer instruction fields are replicated 252 times, defining each of the sequencer’s 252 possible index addresses.
Many sequences can be stored in the sequencer memory at the same time, with each assigned a unique range of index
addresses. The WSEQ_DELAYn field is used to identify the end-of-sequence position, as described below.
The general definition of the sequencer instruction fields is described as follows, where n denotes the sequencer index
address (valid from 0 to 251):
• WSEQ_DATA_WIDTHn is a 3-bit field that identifies the width of the data block to be written. Note that the maximum
value of this field selects a width of 8 bits; writes to fields that are larger than 8 bits wide must be performed using
two separate operations of the write sequencer.
• WSEQ_ADDRn is a 12-bit field containing the register address in which the data should be written. The applicable
register address is referenced to the base address currently configured for the sequencer—it is calculated as: (base
address * 512) + WSEQ_ADDRn. Note that the base address is configured using the sequencer’s extended
instruction set.
•WSEQ_DELAYn is a 4-bit field that controls the waiting time between the current step and the next step in the
sequence (i.e., the delay occurs after the write in which it was called). The total delay time per step (including
execution) is defined below, giving a useful range of execution/delay times from 3.3
s up to 1 s per step.
If WSEQ_DELAYn = 0x0 or 0xF, the step execution time is 3.3
s
For all other values, the step execution time is 61.44
s x ((2 WSEQ_DELAY) – 1)
Setting this field to 0xF identifies the step as the last in the sequence
• WSEQ_DATA_STARTn is a 4-bit field that identifies the LSB position within the selected control register to which
the data should be written. For example, setting WSEQ_DATA_STARTn = 0100 selects bit [4] as the LSB position
of the data to be written.
•WSEQ_DATAn is an 8-bit field that contains the data to be written to the selected control register. The WSEQ_
DATA_WIDTHn field determines how many of these bits are written to the selected control register; the most
significant bits (above the number indicated by WSEQ_DATA_WIDTHn) are ignored.
The extended instruction set for the write sequencer is accessed by setting WSEQ_MODEn (bit [28]) in the respective
sequencer definition register. The extended instruction set comprises the following functions:
• If bits [31:24] = 0x11, the register base address is set equal to the value contained in bits [23:0].
• If bits [31:16] = 0x12FF, the sequencer performs an unconditional jump to the index location defined in bits [15:0].
The index location is valid in the range 0 to 251 (0x0FB).
• All other settings within the extended instruction set are reserved.
The control field definitions for Step 0 are described in Table 4-109. The equivalent definitions also apply to Step 1 through
Step 251, in the subsequent register address locations.



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