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STM32W108HB Datasheet(PDF) 128 Page - STMicroelectronics |
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STM32W108HB Datasheet(HTML) 128 Page - STMicroelectronics |
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128 / 278 page ![]() Serial interfaces STM32W108HB STM32W108CC STM32W108CB STM32W108CZ 128/278 Doc ID 16252 Rev 14 9.8.3 Serial controller interrupt control register 1 (SCx_ICR) Address offset: 0xA854 (SC1_ICR) and 0xA858 (SC2_ICR) Reset value: 0x0000 0000 Reserved, must be kept at reset value IDLELEVEL: Trigger event configuration to generate the IDLE interrupt TXELEVEL: Trigger event configuration to generate the TXE interrupt RNXNELEVEL: Trigger event configuration to generate the RXNE interrupt 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved IDLE LEVEL TXE LEVEL RXNE LEVEL rw rw rw Bits [31:3] Bit 2 This bit is set and cleared by software. 0: Idle interrupt is generated on edge 1: Idle interrupt is generated on level Bit 1 This bit is set and cleared by software. 0: TXE interrupt is generated on edge 1: TXE interrupt is generated on level Bit 0 This bit is set and cleared by software. 0: RXNE interrupt is generated on edge 1: RXNE interrupt is generated on level |
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