STM32W108HB datasheet(131/278 Pages) STMICROELECTRONICS

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STM32W108HB STM32W108CC STM32W108CB STM32W108CZ

Serial interfaces

Doc ID 16252 Rev 14

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9.9

Serial controller: Serial peripheral interface (SPI) registers

9.9.1

Serial controller SPI status register (SCx_SPISR)

Address offset: 0xC840 (SC1_SPISR) and 0xC040 (SC2_SPISR)

Reset value:

0x0000 0000

Reserved, must be kept at reset value

IDLE: Idle line detected flag

TXE: Transmit data register empty flag (transmitters)

RXNE: Data register not empty flag (receivers)

OVF: Overrun flag

Reserved

IDLE

TXE

RXNE

OVF

Bits [31:4]

Bit 3

This bit is set by hardware when both the transmit FIFO and the transmit serializer are empty.

An interrupt is generated if IDLEIE=1 in the SCx_IER register.

0: No SPI idle line is detected

1: SPI idle line is detected

Bit 2

This bit is set by hardware when the transmit FIFO has space to accept at least one byte. An

interrupt is generated if TXEIE = 1 in the SCx_IER register.

0: SPI FIFO registers not empty

1: SPI FIFO registers empty

Bit 1

This bit is set by hardware when the receiver FIFO contains at least one byte. An interrupt is

generated if RXNEIE=1 in the SCx_IER register.

0: Data is not received

1: Received data is ready to be read

Bit 0

This flag is set by hardware when data are received and the receiver FIFO is full. As a result,

the incoming data are lost. It is cleared by software reading the SCx_DR register. An interrupt

is generated if OVRIE=1 in the SCx_IER register.

0: No overrun error occurred

1: Overrun error occurred

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