STM32W108HB datasheet(159/278 Pages) STMICROELECTRONICS

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STM32W108HB STM32W108CC STM32W108CB STM32W108CZ

General-purpose timers

Doc ID 16252 Rev 14

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10.1.2

Counter modes

Up-counting mode

In up-counting mode, the counter counts from 0 to the auto-reload value (contents of the

TIMx_ARR register), then restarts from 0 and generates a counter overflow event.

An update event can be generated at each counter overflow, by setting the UG bit in the

TIMx_EGR register, or by using the slave mode controller.

Software can disable the update event by setting the UDIS bit in the TIMx_CR1 register, to

avoid updating the shadow registers while writing new values in the buffer registers. No

update event will occur until the UDIS bit is written to 0. Both the counter and the prescalar

counter restart from 0, but the prescale rate does not change. In addition, if the URS bit in

the TIMx_CR1 register is set, setting the UG bit generates an update event but without

setting the UIF flag. Thus no interrupt request is sent. This avoids generating both update

and capture interrupts when clearing the counter on the capture event.

When an update event occurs, the update flag (the UIF bit in the TIMx_SR register) is set

(depending on the URS bit in the TIMx_CR1 register) and the following registers are

updated:

●

The buffer of the prescaler is reloaded with the buffer value (contents of the TIMx_PSC

●

The auto-reload shadow register is updated with the buffer value (TIMx_ARR).

Figure 17, Figure 18, Figure 19, and Figure 20 show some examples of the counter

behavior for different clock frequencies when TIMx_ARR = 0x36.

Figure 17.

Counter timing diagram, internal clock divided by 1

STM32W108HB Datasheet(PDF) 159 Page - STMicroelectronics