STM32W108HB datasheet(161/278 Pages) STMICROELECTRONICS

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STM32W108HB STM32W108CC STM32W108CB STM32W108CZ

General-purpose timers

Doc ID 16252 Rev 14

161/278

Figure 20.

Counter timing diagram, update event when ARPE = 1 (TIMx_ARR

buffered)

Down-counting mode

In down-counting mode, the counter counts from the auto-reload value (contents of the

TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a

counter underflow event.

An update event can be generated at each counter underflow, by setting the UG bit in the

TIMx_EGR register, or by using the slave mode controller). Software can disable the update

event by setting the UDIS bit in the TIMx_CR1 register, to avoid updating the shadow

registers while writing new values in the buffer registers. No update event occurs until the

UDIS bit is written to 0. However, the counter restarts from the current auto-reload value,

whereas the prescalar's counter restarts from 0, but the prescale rate doesn't change.

In addition, if the URS bit in the TIMx_CR1 register is set, setting the UG bit generates an

update event, but without setting the UIF flag. Thus no interrupt request is sent. This avoids

generating both update and capture interrupts when clearing the counter on the capture

event.

When an update event occurs, the update flag (the UIF bit in the TIMx_SR register) is set

(depending on the URS bit in the TIMx_CR1 register) and the following registers are

updated:

●

The prescaler shadow register is reloaded with the buffer value (contents of the

TIMx_PSC register).

●

The auto-reload active register is updated with the buffer value (contents of the

TIMx_ARR register). The auto-reload is updated before the counter is reloaded, so that

the next period is the expected one.

Figure 21 and Figure 22 show some examples of the counter behavior for different clock

frequencies when TIMx_ARR = 0x36.

CNT_EN

Timer clock = CK_CNT

Counter register

Update interrupt flag (UIF)

Counter overflow

Update event (UEV)

01 02 03 04 05 06 07

F1 F2 F3 F4 F5

Auto-reload buffer register

Auto-reload shadow register

Write a new value in TIMx_ARR

CK_PSC

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