STM32W108HB datasheet(162/278 Pages) STMICROELECTRONICS

162 / 278 page

General-purpose timers

STM32W108HB STM32W108CC STM32W108CB STM32W108CZ

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Doc ID 16252 Rev 14

Figure 21.

Counter timing diagram, internal clock divided by 1

Figure 22.

Counter timing diagram, internal clock divided by 4

Center-aligned mode (up/down counting)

In center-aligned mode, the counter counts from 0 to the auto-reload value (contents of the

TIMx_ARR register) - 1 and generates a counter overflow event, then counts from the

autoreload value down to 1 and generates a counter underflow event. Then it restarts

counting from 0.

In this mode, the direction bit (DIR in the TIMx_CR1 register) cannot be written. It is updated

by hardware and gives the current direction of the counter.

The update event can be generated at each counter overflow and at each counter

underflow. Setting the UG bit in the TIMx_EGR register by software or by using the slave

mode controller also generates an update event. In this case, the both the counter and the

prescalar's counter restart counting from 0.

Software can disable the update event by setting the UDIS bit in the TIMx_CR1 register.

This avoids updating the shadow registers while writing new values in the buffer registers.

Then no update event occurs until the UDIS bit has been written to 0. However, the counter

continues counting up and down, based on the current auto-reload value.

CK_INT

CNT_EN

Timer clock = CK_CNT

Counter register

Update interrupt flag (UIF)

Counter underflow (cnt_udf)

Update event (UEV)

35 34 33 32 31 30 2F

04 03 02 01 00

0036

0035

CNT_EN

Timer clock = CK_CNT

Counter register

Update interrupt flag (UIF)

0001

0000

Counter underflow

Update event (UEV)

CK_INT

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