STM32W108HB datasheet(182/278 Pages) STMICROELECTRONICS

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General-purpose timers

STM32W108HB STM32W108CC STM32W108CB STM32W108CZ

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Doc ID 16252 Rev 14

Slave mode: Gated mode

In Gated mode the counter is enabled depending on the level of a selected input.

In the following example, the up-counter counts only when the TI1 input is low:

●

Configure channel 1 to detect low levels on TI1 Configure the input filter duration. In

this example, no filter is required, so IC1F = 0000. The capture prescaler is not used for

triggering, so it is not configured. The CC1S bits select the input capture source only,

CC1S = 01 in the TIMx_CCMR1 register. Write CC1P = 1 in the TIMx_CCER register to

validate the polarity (and detect low level only).

●

Configure the timer in Gated mode by writing SMS = 101 in the TIMx_SMCR register.

Select TI1 as the input source by writing TS = 101 in the TIMx_SMCR register.

●

Enable the counter by writing CEN = 1 in the TIMx_CR1 register. In Gated mode, the

counter does not start if CEN = 0, regardless of the trigger input level.

The counter starts counting on the internal clock as long as TI1 is low and stops as soon as

TI1 becomes high. The TIE flag in the TIMx_SR register is set when the counter starts and

when it stops.

The delay between the rising edge on TI1 and the actual stop of the counter is due to the

resynchronization circuit on the TI1 input.

Figure 42.

Control circuit in Gated mode

Counter clock = CK_CNT = CK_PSC

Counter register

35 36 37 38

32 33

TI1

CNT_EN

TIE

Clear TIE

STM32W108HB Datasheet(PDF) 182 Page - STMicroelectronics