STM32W108HB datasheet(184/278 Pages) STMICROELECTRONICS

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General-purpose timers

STM32W108HB STM32W108CC STM32W108CB STM32W108CZ

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Doc ID 16252 Rev 14

Slave mode: External clock mode 2 + Trigger mode

External clock mode 2 can be used in combination with another slave mode (except external

clock mode 1 and encoder mode). In this case, the ETR signal is used as external clock

input, and another input can be selected as trigger input when operating in reset mode,

gated mode or trigger mode. It is not recommended to select ETR as TRGI through the TS

bits of TIMx_SMCR register.

In the following example, the up-counter is incremented at each rising edge of the ETR

signal as soon as a rising edge of TI1 occurs:

●

Configure the external trigger input circuit by programming the TIMx_SMCR register as

follows:

–

ETF = 0000: no filter.

–

ETPS = 00: prescaler disabled.

–

ETP = 0: detection of rising edges on ETR and ECE = 1 to enable the external

clock mode 2.

●

Configure the channel 1 as follows, to detect rising edges on TI:

–

IC1F = 0000: no filter.

–

The capture prescaler is not used for triggering and does not need to be

configured.

–

CC1S = 01in the TIMx_CCMR1 register to select only the input capture source.

–

CC1P = 0 in the TIMx_CCER register to validate the polarity (and detect rising

edge only).

●

Configure the timer in Trigger mode by writing SMS = 110 in the TIMx_SMCR register.

Select TI1 as the input source by writing TS = 101 in the TIMx_SMCR register.

A rising edge on TI1 enables the counter and sets the TIE flag. The counter then counts on

ETR rising edges.

The delay between the rising edge of the ETR signal and the actual reset of the counter is

due to the resynchronization circuit on ETRP input.

Figure 44.

Control circuit in External clock mode 2 + Trigger mode

Counter clock = CK_CNT = CK_PSC

Counter register

ETR

CEN/CNT_EN

TIE

TI1

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