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STM32W108HB Datasheet(PDF) 187 Page - STMicroelectronics |
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STM32W108HB Datasheet(HTML) 187 Page - STMicroelectronics |
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187 / 278 page ![]() STM32W108HB STM32W108CC STM32W108CB STM32W108CZ General-purpose timers Doc ID 16252 Rev 14 187/278 The next example, synchronizes Timer 1 and Timer 2. Timer 1 is the master and starts from 0. Timer 2 is the slave and starts from 0xE7. The prescaler ratio is the same for both timers. Timer 2 stops when Timer 1 is disabled by writing 0 to the CEN bit in the TIM1_CR1 register: ● Configure Timer 1 in master mode to send its Output Compare Reference (OC1REF) signal as trigger output (MMS = 100 in the TIM1_CR2 register). ● Configure the Timer 1 OC1REF waveform (TIM1_CCMR1 register). ● Configure Timer 2 to get the input trigger from Timer 1 (TS = 000 in the TIM2_SMCR register). ● Configure Timer 2 in gated mode (SMS = 101 in the TIM2_SMCR register). ● Reset Timer 1 by writing 1 in the UG bit (TIM1_EGR register). ● Reset Timer 2 by writing 1 in the UG bit (TIM2_EGR register). ● Initialize Timer 2 to 0xE7 by writing 0xE7 in the Timer 2 counter (TIM2_CNTL). ● Enable Timer 2 by writing 1 in the CEN bit (TIM2_CR1 register). ● Start Timer 1 by writing 1 in the CEN bit (TIM1_CR1 register). ● Stop Timer 1 by writing 0 in the CEN bit (TIM1_CR1 register). Figure 47. Gating Timer 2 with enable of Timer 1 TIE Clear TIE 75 00 01 CK_INT TIM1_CR1 CEN=1 TIM2-CNT 02 TIM1_CNT AB 00 E7 E8 E9 TIMER2-CNT_INIT TIMER2 write CNT[15:0] TIMER1-CNT_INIT |
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