STM32W108HB datasheet(189/278 Pages) STMICROELECTRONICS

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STM32W108HB STM32W108CC STM32W108CB STM32W108CZ

General-purpose timers

Doc ID 16252 Rev 14

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Figure 49.

Triggering Timer 2 with enable of Timer 1

Starting both timers synchronously in response to an external trigger

This example, sets the enable of Timer 1 when its TI1 input rises, and the enable of Timer 2

with the enable of Timer 1. Refer to Figure 45 for connections. To ensure the counters are

aligned, Timer 1 must be configured in master/slave mode (slave with respect to TI1, master

with respect to Timer 2):

●

Configure Timer 1 in master mode to send its Enable as trigger output (MMS = 001 in

the TIM1_CR2 register).

●

Configure Timer 1 slave mode to get the input trigger from TI1 (TS = 100 in the

TIM1_SMCR register).

●

Configure Timer 1 in trigger mode (SMS = 110 in the TIM1_SMCR register).

●

Configure the Timer 1 in master/slave mode by writing MSM = 1 (TIM1_SMCR

●

Configure Timer 2 to get the input trigger from Timer 1 (TS = 000 in the TIM2_SMCR

●

Configure Timer 2 in trigger mode (SMS = 110 in the TIM2_SMCR register).

When a rising edge occurs on TI1 (Timer 1), both counters start counting synchronously on

the internal clock and both timers' TIE flags are set.

Note:

In this example both timers are initialized before starting by setting their respective UG bits.

Both counters starts from 0, but an offset can be inserted between them by writing any of

the counter registers (TIMx_CNT). The master/slave mode inserts a delay between

CNT_EN and CK_PSC on Timer 1.

TIE

Clear TIE

CK_INT

TIM1_CR1 CEN=1

TIM1_CNT

TIM2-CNT

TIMER1-CNT_INIT

TIMER2-CNT_INIT

TIMER2

write CNT[15:0]

STM32W108HB Datasheet(PDF) 189 Page - STMicroelectronics

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