STM32W108HB datasheet(191/278 Pages) STMICROELECTRONICS

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STM32W108HB STM32W108CC STM32W108CB STM32W108CZ

General-purpose timers

Doc ID 16252 Rev 14

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10.1.15

Timer signal descriptions

Internal clock source: connects to STM32W108 peripheral

clock (PCLK) in internal clock mode.

Input to the clock prescaler.

External trigger input (used in external timer mode 2): a clock

selected by EXTRIGSEL in TIMx_OR.

External trigger: ETRP after filtering.

External trigger: ETR after polarity selection, edge detection

and prescaling.

Input capture or clock: TIy after filtering and edge detection.

Input capture signal after filtering, edge detection and

prescaling: input to the capture register.

Internal trigger input: connected to the other timer's output,

TRGO.

Output compare: TIMxCy when used as an output. Same as

OCyREF but includes possible polarity inversion.

Output compare reference: always active high, but may be

inverted to produce OCy.

Peripheral clock connects to CK_INT and used to clock input

filtering. Its frequency is 12 MHz if using the 24 MHz HSE

OSC and 6 Mhz if using the 12 MHz HSI RC oscillator.

Timer input: TIMxCy when used as a timer input.

Timer input after filtering and polarity selection.

Timer channel at a GPIO pin: can be a capture input (ICy) or

a compare output (OCy).

Clock input (if selected) to the external trigger signal (ETR).

Clock mask (if enabled) AND'ed with the other timer's

TIMxCLK signal.

Trigger input for slave mode controller.

Table 35.

Timer signal descriptions

Signal

Internal/external

Description

CK_INT

Internal

CK_PSC

Internal

ETR

Internal

ETRF

Internal

ETRP

Internal

ICy

External

ICyPS

Internal

ITR0

Internal

OCy

External

OCyREF

Internal

PCLK

External

TIy

Internal

TIyFPy

Internal

TIMxCy

Internal

TIMxCLK

External

TIMxMSK

External

TRGI

Internal

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