STM32W108HB datasheet(194/278 Pages) STMICROELECTRONICS

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General-purpose timers

STM32W108HB STM32W108CC STM32W108CB STM32W108CZ

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Doc ID 16252 Rev 14

10.3.4

Timer x control register 1 (TIMx_CR1)

Address offset: 0xE000 (TIM1) and 0xF000 (TIM2)

Reset value:

0x0000 0000

Reserved

ARPE

CMS[1:0]

DIR

OPM

URS

UDIS

CEN

Bits [31:8] Reserved, must be kept at reset value

Bit 7 ARPE: Auto-Reload Preload Enable

0: TIMx_ARR register is not buffered

1: TIMx_ARR register is buffered

Bits [6:5] CMS[1:0]: Center-aligned Mode Selection

00: Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR).

01: Center-aligned mode 1. The counter counts up and down alternatively.

Output compare interrupt flags of configured output channels (CCyS=00 in TIMx_CCMRy

10: Center-aligned mode 2. The counter counts up and down alternatively.

Output compare interrupt flags of configured output channels (CCyS=00 in TIMx_CCMRy

11: Center-aligned mode 3. The counter counts up and down alternatively.

Output compare interrupt flags of configured output channels (CCyS=00 in TIMx_CCMRy

Note: Software may not switch from edge-aligned mode to center-aligned mode when the

counter is enabled (CEN=1).

Bit 4 DIR: Direction

0: Counter used as up-counter

1: Counter used as down-counter

Bit 3 OPM: One Pulse Mode

0: Counter does not stop counting at the next update event.

1: Counter stops counting at the next update event (and clears the bit CEN).

Bit 2 URS: Update Request Source

0: When enabled, update interrupt requests are sent as soon as registers are updated

(counter overflow/underflow, setting the UG bit, or update generation through the slave mode

controller).

1: When enabled, update interrupt requests are sent only when the counter reaches overflow

or underflow.

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