STM32W108HB datasheet(196/278 Pages) STMICROELECTRONICS

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General-purpose timers

STM32W108HB STM32W108CC STM32W108CB STM32W108CZ

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Doc ID 16252 Rev 14

10.3.5

Timer x control register 2 (TIMx_CR2)

Address offset: 0xE004 (TIM1) and 0xF004 (TIM2)

Reset value:

0x0000 0000

Reserved, must be kept at reset value

TI1S: TI1 Selection

MMS[2:0]: Master Mode Selection

Reserved, must be kept at reset value

Reserved

TI1S

MMS[2:0]

Reserved

Bits [31:8]

Bit 7

0: TI1M (input of the digital filter) is connected to TI1 input.

1: TI1M is connected to the TI_HALL inputs (XOR combination).

Bits [6:4]

This selects the information to be sent in master mode to a slave timer for synchronization

using the trigger output (TRGO).

000: Reset - the UG bit in the TIMx_EGR register is trigger output.

If the reset is generated by the trigger input (slave mode controller configured in reset mode),

then the signal on TRGO is delayed compared to the actual reset.

001: Enable - counter enable signal CNT_EN is trigger output.

This mode is used to start both timers at the same time or to control a window in which a

slave timer is enabled. The counter enable signal is generated by either the CEN control bit or

the trigger input when configured in gated mode. When the counter enable signal is

controlled by the trigger input there is a delay on TRGO except if the master/slave mode is

selected (see the MSM bit description in TIMx_SMCR register).

010: Update - update event is trigger output

This mode allows a master timer to be a prescaler for a slave timer.

011: Compare Pulse

The trigger output sends a positive pulse when the CC1IF flag is to be set (even if it was

already high) as soon as a capture or a compare match occurs.

100: Compare - OC1REF signal is trigger output

101: Compare - OC2REF signal is trigger output

110: Compare - OC3REF signal is trigger output

111: Compare - OC4REF signal is trigger output

Bits [3:0]

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