STM32W108HB datasheet(199/278 Pages) STMICROELECTRONICS

199 / 278 page

STM32W108HB STM32W108CC STM32W108CB STM32W108CZ

General-purpose timers

Doc ID 16252 Rev 14

199/278

Bits [2:0] SMS[2:0]: Slave Mode Selection

When external signals are selected the active edge of the trigger signal (TRGI) is linked to

the polarity selected on the external input.

000: Slave mode disabled.

If CEN = 1 then the prescaler is clocked directly by the internal clock.

001: Encoder mode 1. Counter counts up/down on TI1FP1 edge depending on TI2FP2 level.

010: Encoder mode 2. Counter counts up/down on TI2FP2 edge depending on TI1FP1 level.

011: Encoder mode 3. Counter counts up/down on both TI1FP1 and TI2FP2 edges

depending on the level of the other input.

100: Reset Mode. Rising edge of the selected trigger signal (TRGI) >reinitializes the counter

and generates an update of the registers.

101: Gated Mode. The counter clock is enabled when the trigger signal (TRGI) is high. The

counter stops (but is not reset) as soon as the trigger becomes low. Both starting and

stopping the counter are controlled.

110: Trigger Mode. The counter starts at a rising edge of the trigger TRGI (but it is not reset).

Only starting the counter is controlled.

111: External Clock Mode 1. Rising edges of the selected trigger (TRGI) clock the counter.

Note: Gated mode must not be used if TI1F_ED is selected as the trigger input (TS=100).

TI1F_ED outputs 1 pulse for each transition on TI1F, whereas gated mode checks the level of

the trigger signal.

STM32W108HB Datasheet(PDF) 199 Page - STMicroelectronics