STM32W108HB datasheet(197/278 Pages) STMICROELECTRONICS

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STM32W108HB STM32W108CC STM32W108CB STM32W108CZ

General-purpose timers

Doc ID 16252 Rev 14

197/278

10.3.6

Timer x slave mode control register (TIMx_SMCR)

Address offset: 0xE008 (TIM1) and 0xF008 (TIM2)

Reset value:

0x0000 0000

Reserved

ETP

ECE

ETPS[1:0]

ETF[3:0]

MSM

TS[2:0]

Reserved

SMS[2:0]

Bits [31:16] Reserved, must be kept at reset value

Bit 15 ETP: External Trigger Polarity

This bit selects whether ETR or the inverse of ETR is used for trigger operations.

0: ETR is non-inverted, active at a high level or rising edge

1: ETR is inverted, active at a low level or falling edge

Bit 14 ECE: External Clock Enable

This bit enables external clock mode 2.

0: External clock mode 2 disabled

1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF

signal.

Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI

connected to ETRF (SMS=111 and TS=111). It is possible to use this mode simultaneously

with the following slave modes: reset mode, gated mode and trigger mode. TRGI must not be

connected to ETRF in this case (the TS bits must not be 111). If external clock mode 1 and

external clock mode 2 are enabled at the same time, the external clock input will be ETRF.

Bits [13:12] ETPS[1:0]: External Trigger Prescaler

External trigger signal ETRP frequency must be at most 1/4 of CK frequency. A prescaler

can be enabled to reduce ETRP frequency. It is useful with fast external clocks.

00: ETRP prescaler off

01: Divide ETRP frequency by 2

10: Divide ETRP frequency by 4

11: Divide ETRP frequency by 8

STM32W108HB Datasheet(PDF) 197 Page - STMicroelectronics