STM32W108HB datasheet(192/278 Pages) STMICROELECTRONICS

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General-purpose timers

STM32W108HB STM32W108CC STM32W108CB STM32W108CZ

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Doc ID 16252 Rev 14

10.2

Interrupts

Several kinds of timer events can generate a timer interrupt, and each has a status flag in

the TIMx_SR register to identify the reason(s) for the interrupt:

●

TIE - set by a rising edge on an external trigger, either edge in gated mode

●

CCyIF - set by a channel y input capture or output compare event

●

UIF - set by an update event

Clear bits in TIMx_SR by writing a 1 to their bit position. When a channel is in capture mode,

reading the TIMx_CCRy register will also clear the CCyIF bit.

The TIMx_IER register controls whether or not the TIMx_SR bits actually request an ARM®

Cortex-M3 timer interrupt. Only the events whose bits are set to 1 in TIMx_IER can do so.

If an input capture or output compare event occurs and its CCyIM is already set, the

corresponding capture/compare missed flag is set in the TIMx_MISSR register. Clear a bit in

the TIMx_MISSR register by writing a 1 to it.

10.3

General-purpose timers 1 and 2 registers

10.3.1

Timer x interrupt and status register (TIMx_ISR)

Address offset: 0xA800 (TIM1) and 0xA804 (TIM2)

Reset value:

0x0000 0000

Reserved, must be kept at reset value

RSVD[3:0]: May change during normal operation

Reserved, must be kept at reset value

TIF: Trigger interrupt

Reserved, must be kept at reset value

CC4IF: Capture or compare 4 interrupt pending

CC3IF: Capture or compare 3 interrupt pending

CC2IF: Capture or compare 2 interrupt pending

CC1IF: Capture or compare 1 interrupt pending

UIF: Update interrupt pending

Reserved

RSVD[3:0]

Reserved

TIF

Reserved

CC4IF

CC3IF

CC2IF

CC1IF

UIF

rrr

Bits [31:13]

Bits [12:9]

Bits [8:7]

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

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